raju_kambar
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Dear Sir,
(1) I have taken ATF 54143 transistor. It is 4 pin IC , two sources are present diagonally opposite to each other. When I connected capacitors and VIAS two sides of the two sources of the ATF 54143 transistor and generated layout. In layout generation, ATF 54143 transistor layout generated, two sources are generating side by side. Sources are not generating diagonally opposite to each other, they are adjacent to each other in the layout generation. How to generate the ATF 54143 transistor two sources diagonally opposite to each other. One more thing physically transistors two sources are diagonally opposite to each other, if layout generation comes side by side two sources, while fabrication it is difficulty. I have shown below the images of Scheamtic_LAYOUT and Generated_layout.
(2) One more difficulty, I have. I want to generate the two layers top layer and bottom layers in layout generation. I want to connect the VIA HOLE from top layer to bottom layer . How we can generate bottom and top layers in ADS 2009 and how we can connect the VIA HOLE from top to bottom layer through the substrate. I have noticed in the example from C:\ADS2009\examples\MW_Ckts\LNA_1GHz_prj, but they didn't use the VIA HOLE connection and bottom conductor. My question is , how to generate the top and bottom layers and connect the VIA HOLE from top to bottom through the substrate with some thickness , and also how to view the 3-dimesional view for top layer , bottom layer. Can you help me to sort out these difficulty.
(1) I have taken ATF 54143 transistor. It is 4 pin IC , two sources are present diagonally opposite to each other. When I connected capacitors and VIAS two sides of the two sources of the ATF 54143 transistor and generated layout. In layout generation, ATF 54143 transistor layout generated, two sources are generating side by side. Sources are not generating diagonally opposite to each other, they are adjacent to each other in the layout generation. How to generate the ATF 54143 transistor two sources diagonally opposite to each other. One more thing physically transistors two sources are diagonally opposite to each other, if layout generation comes side by side two sources, while fabrication it is difficulty. I have shown below the images of Scheamtic_LAYOUT and Generated_layout.
(2) One more difficulty, I have. I want to generate the two layers top layer and bottom layers in layout generation. I want to connect the VIA HOLE from top layer to bottom layer . How we can generate bottom and top layers in ADS 2009 and how we can connect the VIA HOLE from top to bottom layer through the substrate. I have noticed in the example from C:\ADS2009\examples\MW_Ckts\LNA_1GHz_prj, but they didn't use the VIA HOLE connection and bottom conductor. My question is , how to generate the top and bottom layers and connect the VIA HOLE from top to bottom through the substrate with some thickness , and also how to view the 3-dimesional view for top layer , bottom layer. Can you help me to sort out these difficulty.