Problems when synthesizing Verilog codes in Synplyfy Pro

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kiki_liu

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SOS in synplyfy pro

hey, guys, i got a problem and can not find the reason
i use the device of ALTERA STRATIX, use the part of EPIS80, speed is 7 and the package is FC1508 in syplyfy pro 7.1.
when i systhesis my verilog code, i got several warnnings of "Removing sequential instance .delname of view: ALTERA_APEX .S_DFF(PRIM) because there are no reference to its outputs", i did not get the meaning, cause i check every register in the schematic level, but no register's output are non-use.
and there is no any warnings when i systhesis using other kinds of device, like xilinx.
could you guys give me some hints? thank you so much.
all have a nice day
best regards
 

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