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Problems when compiling VHDL files

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tybhsl

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When I try to compile the file of icache.vhd in leon2.0
using Active-HDL 5.1 instead of ModSim in which no error is reported, some errors are reported as the following:

case ISETS is
when 2 =>
...
Line98 when 3 =>
Line99 if ICLOCK_BIT = 1 then
Line100 xset := std_logic_vector(conv_unsigned(lru3_repl_table
conv_integer(xlru)) (unlocked), 2));
Line101 else
Line102 xset := std_logic_vector(conv_unsigned(lru3_repl_table
(conv_integer(xlru)) (0), 2));
end if;
when 4 =>
....
when others =>
end case;


Error: COMP96_0368: icache.vhd : (98, 8): Value 3 out of range.
Error: COMP96_0149: icache.vhd : (100, 32): Explicit type conversion are allowed between closely related types only.
Error: COMP96_0149: icache.vhd : (102, 32): Explicit type conversion are allowed between closely related types only.

Could you please tell me what should I do? How can I simulate it with the tool of Active-HDL 5.1 but ModSim? Thank you very much!
 

veejaye

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Check the Declaration of ISETS....
It should be declared as integer with range more than 4......

What is this lru3_repl_table?
Is it a function or a procedure.
If u r using some library functions check wether the library is included.
Conv_unsigned can be omited by simply adding
use ieee.std_logic_unsigned.all.....
 

tybhsl

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Error: COMP96_0149: icache.vhd : (100, 32): Explicit type conversion are allowed between closely related types only.
Error: COMP96_0149: icache.vhd : (102, 32): Explicit type conversion are allowed between closely related types only.
solved by adding " ieee.std_logic_arth.all". Thank you very much!

but
Error: COMP96_0368: icache.vhd : (98, : Value 3 out of range.
still exists.

ISETS is declared as constant integer with range 1 to 4 in a package compiled as a library ......

can you give more advice on how to solve this problem? Thanks!
 

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