jayh
Newbie level 6
here is our flow
1. RTL
2. R2N netlist by synthesis(input: RTL/output: R2N)
3. a simple script to add some MUX on DFT clock path(input: R2N/output :R2N_DFT)
4. N2N netlist by resyntheis(input :R2N_DFT/output :N2N)
the problems is :
RTL LEC R2N: OK
RTL LEC R2N_DFT: OK
R2N_DFT LEC N2N : OK
RTL LEC N2N : NG
Test mode signal is kept inactive with LEC, so step 3 has no impact to logic(test path disabled) and just USER path verified.
i checked the umremap log, but it seems difficult to find hints
could anybody give me some hints or direction?
1 VS 2 OK and 2 VS 3 OK
can we judge 1 VS 3 OK?
thanks
1. RTL
2. R2N netlist by synthesis(input: RTL/output: R2N)
3. a simple script to add some MUX on DFT clock path(input: R2N/output :R2N_DFT)
4. N2N netlist by resyntheis(input :R2N_DFT/output :N2N)
the problems is :
RTL LEC R2N: OK
RTL LEC R2N_DFT: OK
R2N_DFT LEC N2N : OK
RTL LEC N2N : NG
Test mode signal is kept inactive with LEC, so step 3 has no impact to logic(test path disabled) and just USER path verified.
i checked the umremap log, but it seems difficult to find hints
could anybody give me some hints or direction?
1 VS 2 OK and 2 VS 3 OK
can we judge 1 VS 3 OK?
thanks