Problems in simulation,rtl viewer,synthesis report

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kannan2590

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Although if some blocks in the rtl view is missing there are some warning messages in the synthesis report i get correct output in the simulation result.I have simulated all the modules together .Then where is the issue in the code .
 

Yes i have the code

for polyphase


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity polyphase is
Port ( clk : in STD_LOGIC;

clk_120mbps: in std_logic;
reset : in STD_LOGIC;
din : in STD_LOGIC_vector(7 downto 0);
ifiltout : out STD_LOGIC_vector(23 downto 0)
);
end polyphase;

architecture Behavioral of polyphase is

component subfilta
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;

component subfiltb
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltc
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltd
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfilte
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltf
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltg
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfilth
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfilti
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;

component subfiltj
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;

component subfiltk
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltl
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltm
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
------
component subfiltn
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfilto
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltp
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;

component subfiltq
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;

component subfiltr
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfilts
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltt
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltu
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltv
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltw
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltx
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfilty
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;

component subfiltz
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;

component subfiltaa
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltbb
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltcc
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
----
component subfiltdd
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltee
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;
--
component subfiltff
port( doutut std_logic_vector(23 downto 0);
clk:in std_logic;

reset:in std_logic;
din:in std_logic_vector(7 downto 0)
);
end component;


signal ifilterout0,ifilterout1,ifilterout2,ifilterout3:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout4,ifilterout5,ifilterout6,ifilterout7:STD_LOGIC_vector(23 downto 0):=(others =>'0');

signal ifilterout8,ifilterout9,ifilterout10,ifilterout11:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout12,ifilterout13,ifilterout14,ifilterout15:STD_LOGIC_vector(23 downto 0):=(others =>'0');

signal ifilterout16,ifilterout17,ifilterout18,ifilterout19:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout20,ifilterout21,ifilterout22,ifilterout23:STD_LOGIC_vector(23 downto 0):=(others =>'0');

signal ifilterout24,ifilterout25,ifilterout26,ifilterout27:STD_LOGIC_vector(23 downto 0):=(others =>'0');
signal ifilterout28,ifilterout29,ifilterout30,ifilterout31:STD_LOGIC_vector(23 downto 0):=(others =>'0');
--

begin
subfilt0a: subfilta port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout0);
subfilt0b: subfiltb port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout1);
subfilt0c: subfiltc port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout2);
subfilt0d: subfiltd port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout3);
subfilt0e: subfilte port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout4);
subfilt0f: subfiltf port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout5);
subfilt0g: subfiltg port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout6);
subfilt0h: subfilth port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout7);

subfilt0i: subfilti port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout8);
subfilt0j: subfiltj port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout9);
subfilt0k: subfiltk port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout10);
subfilt0l: subfiltl port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout11);
subfilt0m: subfiltm port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout12);
subfilt0n: subfiltn port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout13);
subfilt0o: subfilto port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout14);
subfilt0p: subfiltp port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout15);

subfilt0q: subfiltq port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout16);
subfilt0r: subfiltr port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout17);
subfilt0s: subfilts port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout18);
subfilt0t: subfiltt port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout19);
subfilt0u: subfiltu port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout20);
subfilt0v: subfiltv port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout21);
subfilt0w: subfiltw port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout22);
subfilt0x: subfiltx port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout23);

subfilt0y: subfilty port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout24);
subfilt0z: subfiltz port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout25);
subfilt0aa: subfiltaa port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout26);
subfilt0bb: subfiltbb port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout27);
subfilt0cc: subfiltcc port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout28);
subfilt0dd: subfiltdd port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout29);
subfilt0ee: subfiltee port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout30);
subfilt0ff: subfiltff port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout31);

--
P20ROCESS(clk_120mbps,RESET)
VARIABLE CNT:STD_LOGIC_VECTOR(5 DOWNTO 0):="000000";
BEGIN


IF RESET='0' THEN
CNT:="000000";
ifiltout <=(others =>'0');
ELSIF clk_120mbps='1' AND clk_120mbps'EVENT THEN
CNT := CNT +1;
CASE CNT IS
WHEN "000001"=> ifiltout <=ifilterout0;
WHEN "000010"=> ifiltout <=ifilterout1;
WHEN "000011"=> ifiltout <=ifilterout2;
WHEN "000100"=> ifiltout <=ifilterout3;
WHEN "000101"=> ifiltout <=ifilterout4;
WHEN "000110"=> ifiltout <=ifilterout5;

WHEN "000111"=> ifiltout <=ifilterout6;
WHEN "001000"=> ifiltout <=ifilterout7;

WHEN "001001"=> ifiltout <=ifilterout8;
WHEN "001010"=> ifiltout <=ifilterout9;
WHEN "001011"=> ifiltout <=ifilterout10;
WHEN "001100"=> ifiltout <=ifilterout11;
WHEN "001101"=> ifiltout <=ifilterout12;
WHEN "001110"=> ifiltout <=ifilterout13;
----
WHEN "001111"=> ifiltout <=ifilterout14;
WHEN "010000"=> ifiltout <=ifilterout15;

WHEN "010001"=> ifiltout <=ifilterout16;
WHEN "010010"=> ifiltout <=ifilterout17;
WHEN "010011"=> ifiltout <=ifilterout18;
WHEN "010100"=> ifiltout <=ifilterout19;
WHEN "010101"=> ifiltout <=ifilterout20;
WHEN "010110"=> ifiltout <=ifilterout21;

WHEN "010111"=> ifiltout <=ifilterout22;
WHEN "011000"=> ifiltout <=ifilterout23;

WHEN "011001"=> ifiltout <=ifilterout24;
WHEN "011010"=> ifiltout <=ifilterout25;
WHEN "011011"=> ifiltout <=ifilterout26;
WHEN "011100"=> ifiltout <=ifilterout27;
WHEN "011101"=> ifiltout <=ifilterout28;
WHEN "011110"=> ifiltout <=ifilterout29;

WHEN "011111"=> ifiltout <=ifilterout30;
WHEN "100000"=> ifiltout <=ifilterout31;
--

--
CNT := "000000";

WHEN OTHERS => ifiltout <="000000000000000000000000";
END CASE;
--CNT <= CNT +1;
END IF;
END PROCESS P20;



end Behavioral;


i cannot post the entire subfilter files .i AM providing only 2 subfilters files


FOR subfilta

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity subfilta is
Port ( dout : out STD_LOGIC_vector(23 downto 0);
clk : in STD_LOGIC;

reset : in STD_LOGIC;
din : in STD_LOGIC_vector(7 downto 0));
end subfilta;

architecture Behavioral of subfilta is

--component DFF is
-- port(
-- q : out STD_LOGIC_vector(27 downto 0); --output connected to the adder
-- Clk :in std_logic; -- Clock input
-- d :in STD_LOGIC_vector(27 downto 0) -- Data input from the MCM block.
-- );
--end component;

component DFFa is
port(
q : out STD_LOGIC_vector(7 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
d :in STD_LOGIC_vector(7 downto 0) -- Data input from the MCM block.
);
end component;



signal H00,H032,H064 : STD_LOGIC_vector(15 downto 0) := (others => '0');
--signal MCM00,MCM01,MCM02,MCM03 : STD_LOGIC_vector(31 downto 0) := (others => '0');
signal add_out01: STD_LOGIC_vector(23 downto 0) := (others => '0');
--signal Q01,Q02,Q03 : STD_LOGIC_vector(31 downto 0) := (others => '0');
signal din1,din2:std_logic_vector(7 downto 0):=(others =>'0');
--signal Q0100 : STD_LOGIC_vector(27 downto 0) := (others => '0');
--signal Q01000 : STD_LOGIC_vector(27 downto 0) := (others => '0');
begin

H00 <= "1111110110101011";

H032<= "0011111010011010";

H064<= "0000001100010010";

add_out01 <=(din*H00)+(din1*H032)+(din2*H064);

dffaa : DFFa port map(q=>din1,clk=>clk,d=>din);
dffbb : DFFa port map(q=>din2,clk=>clk,d=>din1);



p01000rocess(Clk,reset)
begin
if reset='0' then
dout <= "000000000000000000000000";
elsif clk'event and clk='1' then

dout <= add_out01;

end if;
end process p01000;



end Behavioral;


for DFFA code is as below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DFFa is
Port ( Q : out std_logic_vector(7 downto 0);
CLK : in STD_LOGIC;

D : in std_logic_vector(7 downto 0));
end DFFa;

architecture Behavioral of DFFa is


signal qt1 : std_logic_vector(7 downto 0) := (others => '0');

begin

Q <= qt1;
--
p10rocess(Clk)
begin
if ( rising_edge(Clk) ) then
qt1 <= D;
end if;




end process p10;



end Behavioral;
 

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