syedshan
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Hello all,
I generated FIFO core using Xilinx core generator and following is the specs.
Following are core specs
1. input data width is 16 bits
2. output data width is 64 bits
3. For now, both read and write clock are similar, same frequency etc.
Now I have following issues.
1. The Full and almost full signals should be LOW when RST is applied
2. Even after several clock after RST de-asserted , The FIFO empty signal does not goes low. The consequence is that those initial 3 data are lost.
I cannot understand why is this happening. As I remember this thing I also faced earlier and find the solution as well which was quite easy but I cannot remember it now
Bests,
Shan
- - - Updated - - -
Oh I later found the solution.
It is by setting Full Flag programmable values to '0'
When set to '1' gives the result as I was getting
I generated FIFO core using Xilinx core generator and following is the specs.
Following are core specs
1. input data width is 16 bits
2. output data width is 64 bits
3. For now, both read and write clock are similar, same frequency etc.
Now I have following issues.
1. The Full and almost full signals should be LOW when RST is applied
2. Even after several clock after RST de-asserted , The FIFO empty signal does not goes low. The consequence is that those initial 3 data are lost.
I cannot understand why is this happening. As I remember this thing I also faced earlier and find the solution as well which was quite easy but I cannot remember it now
Bests,
Shan
- - - Updated - - -
Oh I later found the solution.
It is by setting Full Flag programmable values to '0'
When set to '1' gives the result as I was getting
Last edited:
