problems facing in closed loop control

[biswaIITH]

Hello frnds..i am designing 1-phase PFC rectifier(a bridge rectifier+DC-DC converter)..I m doing closed loop control using SG3525...I am using 3 NTCs in series(60 ohm total,4A) for inrush current protection...I have given 5 v reference(pin-2,non-inverting input) in SG3525...

Following are my specification
Input voltage-100Vpeak
Output voltage-30V
Output load=60ohm..
operating switching frequency=47KHz

Below attached is the results and the main system...
as u can see
1)WHY does the input current contain a lot of spikes and not in phase with input voltage???...

2)WHY is the load voltage not increasing beyond 5V ???

3)WHY r Pulses from SG3525 getting distorted under rated condition???

 

[E-design]

Maybe you should show a more detailed circuit diagram as I can't see how you want to achieve PFC with this.

 

[red_alert]

Seems like SG3525 has drastically reduced its duty cycle.

Maybe you have connected the output to SG3525 feedback pin (IN-) directly (without a voltage divider). That could explain the output voltage (5 V) and the reduced duty ratio (a normal value for such a low output voltage).

Double check the feedback circuit (or post its schematic for further help).

 

[schmitt trigger]

A PFC controller with a SG3525?
Really??
How are you achieving the necessary multiplication of the input waveform and the voltage feedback?

Without a detailed schematic people here will be only guessing what is going on.

 

[biswaIITH]

The dc-dc converter in the schematic is being operated in discontinuous conduction mode..As the dc-dc converter is buck-boost integrated buck converter(i.e. buck-boost is the first stage and buck is the second),it has inherent input current shaping property..so no need of multiplication...U just have to control the load voltage..That is why i am using SG3525...

 

[schmitt trigger]

The dc-dc converter in the schematic is being operated in discontinuous conduction mode..As the dc-dc converter is buck-boost integrated buck converter(i.e. buck-boost is the first stage and buck is the second),it has inherent input current shaping property..so no need of multiplication...U just have to control the load voltage..That is why i am using SG3525...

I would like to be educated, as I've never seen such a scheme. Not saying that is not possible, only that I've never seen it.

Maybe there is an assumption you made which is causing your problem.
But with no schematic, no board layout and no photos provided, it is impossible for forum members to provide meaningful help.

 

[BradtheRad]

Your Cf capacitor is only 1 uF. The waveform going into the buck converter is not smooth.

Increase its value to 100 uF.

 

[biswaIITH]

Your Cf capacitor is only 1 uF. The waveform going into the buck converter is not smooth.

Increase its value to 100 uF.

Sir, as i have mentioned in the previous post...The dc-dc converter in schematic is a (buck-boost + buck) converter.The first stage is buck-boost and the second stage is buck...Both are being operated in discontinuous conduction mode...I have done the simulation in matlab simulink with the exact filter components(i mean values),there it was perfectly working(the input current is perfectly sinusoidal and in phase with supply voltage)...
And one more thing,the capacitor(Cf) i am using is an AC capacitor (400V rating)...I have simulated using 100uF in simulation, it is showing error in simulink....

- - - Updated - - -

I would like to be educated, as I've never seen such a scheme. Not saying that is not possible, only that I've never seen it.

Maybe there is an assumption you made which is causing your problem.
But with no schematic, no board layout and no photos provided, it is impossible for forum members to provide meaningful help.

Sir, thanks for ur kind reply..As i posted earlier the dc-dc converter mentioned in the schematics is a (buck-boost +buck)...The first stage is a buck-boost and second stage is a buck..Both the stages are being operated in discontinuous conduction mode...Now if we operate a buck-boost converter in DCM, it has inherent PFC capabillity..U can find that by calculating the average input current to a buck-boost converter(operated in DCM),in which case u will find that the Iavg=(some constant)*V..
i.e. the input impedance will behave like a resistor thereby improving the PF...u can get plenty of publications using Buck-boost as a PFC converter...
There u can see ,if the first stage has inherent PFC capabillity then the current loop can be eliminated..Only voltage loop for controlling the load voltage will be required...

Now if u operate the converter in CCM,it will loose its inherent PFC capabillity..In that case ,to make the input current sinusoidal and in phase with the supply voltage ,we will require both current as well as voltage loops

 

[FvM]

I fear the need to clear up misunderstandings is mostly brought up by not revealing your circuit details. Although you mentioned it in your posts in passing, it's not obvious from the start that the "DC/DC-converter" is actually two converters with an intermediate energy storage.

But even if I can roughly guess what's in the box, I can't answer your questions in post #1 as long as I don't see the schematic. E.g. why is the output voltage not increasing beyond 5 V? - Because it's designed as it is?

 

[biswaIITH]

Hello folks..i have checked the circuit..The problems was due to damage in the feedback voltage divider resistor...Today i have taken 3 observations at 3 different input voltage levels with 30V desired output voltage...

As u can see ,i have taken reading for 110Vrms,77Vrms and with a slightly lower voltage arnd 40 Vrms...In the first 2 cases i am not getting the exact load voltage ,but that can be achieved through compensation which i havenot applied in SG3525 yet
My question is why the input current waveform contains high spikes as the input voltage increases...Is it because of the improper input filter design????

 

[schmitt trigger]

Thanks for the info.

The voltage spikes are always caused by either:
1) Too high ESR/ESL on the filter components
2) Parasitic capacitance/ inductance in resonance.

Both are layout and actual component dependent.

 

[biswaIITH]

Thanks for the info.

The voltage spikes are always caused by either:
1) Too high ESR/ESL on the filter components
2) Parasitic capacitance/ inductance in resonance.

Both are layout and actual component dependent.

So what should i do??shall i use EMI filters available in the market???
one more thing i forgot to mention...i havent designed my testing circuit in PCB....i am using a general purpose board for designing it...Is it causing unnecessary EMI as my switching frequency is high(47 KHz)???

 

[schmitt trigger]

one more thing i forgot to mention...i havent designed my testing circuit in PCB....i am using a general purpose board for designing it...Is it causing unnecessary EMI as my switching frequency is high(47 KHz)???

That's it!

 

[biswaIITH]

That's it!

So shall i buy EMI filter available in market and use it??
Will it be effective in the current design(i.e. in the general purpose board)???

 

[schmitt trigger]

No.
Good layout is half of your circuit design.

You can breadboard a basic concept, but for the final circuit, you will have to jump to a board.

 

[FvM]

I agree with schmitt trigger that it's unrealistic to expect low EMI from a stripboard setup.

Secondly, EMI may be promoted by your specific circuit topology. You didn't yet reveal in the forum how your buck-boost PFC stage looks like but it may involve more switching transients fed to the input than a conventional boost PFC which has a series inductor that enforces a continuous input current. This point can be only analyzed if you show the circuit.

 

[FvM]

A cunning circuit. But diode reverse recovery peaks are directly coupled to the input side.
There's no such thing as a free lunch.

 

[biswaIITH]

"There is no such thing as a free lunch"...With all due respect but i dont get this particular line

 

[red_alert]

"everything in the world has a drawback".. that's a wise old saying.. or a Murphy law.

 

[FvM]

The "free lunch" saying is quite often quoted at Edaboard when talking about design trade-offs.

It this case, it means that the tricky topology most likely involves higher EMI than industry standard PFC designs. There's a reason why commercial PFC power supplies use a different topology.