Because initially you are writing a Mealy FSM, which your output Dout depends on current state and current input Din. When Din changes to 1 (1->0->1) and current state is St2, Dout will goes high. In this case, your testbench code changes Din to 1 at the falling edge of clk, so u see Dout being 1 at falling edge.You can change your testbench to make it happens at rising edge.
When you change to MOORE FSM, output Dout depending on current state(rising edge) works like what you want.