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problem with VHDL mealy sequence detector

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Armand86

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hello, i need help with VHDL sequence detector (101) project. I wrote VHDL file but output dout goes to 1 when machine is on "Next state" and not on "Present state". In other words machine gives output 1 on the falling edge of clock and not rising edge. anyone can help me? thanks



Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity riconoscitoremealy is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end riconoscitoremealy;
architecture Behavioral of riconoscitoremealy is
type state is (st0, st1, st2);
signal present_state, next_state : state;
begin
syncronous_process : process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
next_state_and_output_decoder : process(present_state, din)
begin
dout <= '0';
case (present_state) is
when st0 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st0;
dout <= '0';
end if;
when St1 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st2;
dout <= '0';
end if;
when St2 =>
if (din = '1') then
next_state <= st1;
dout <= '1';
else
next_state <= st0;
dout <= '0';
end if;
when others =>
next_state <= st0;
dout <= '0';
end case;
end process;
end Behavioral;


Schermata 2017-09-01 alle 20.39.59.png
 

ThisIsNotSam

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learn the difference between modelling sequential and combinational logic. next_state is combinational, state is sequential. next_state updates immediately upon a change on the inputs. state waits until the next clock edge to capture data.
 

TrickyDicky

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thats because dout is combinatorial, and from your code is reduced to this one liner code:

dout <= '1' when present_state = St2 and din = '1' else '0';
 

Armand86

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i have made the same machine with Moore and it works perfectly, why?
 

fpga4student

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Because initially you are writing a Mealy FSM, which your output Dout depends on current state and current input Din. When Din changes to 1 (1->0->1) and current state is St2, Dout will goes high. In this case, your testbench code changes Din to 1 at the falling edge of clk, so u see Dout being 1 at falling edge.You can change your testbench to make it happens at rising edge.
When you change to MOORE FSM, output Dout depending on current state(rising edge) works like what you want.
 

Armand86

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i am not very skilled with VHDL code, can you show me how to modify mine? solution with testbench seems not to work well. Thanks
 

fpga4student

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You have to understand the fundamental of Mealy and Moore FSM. If you want Dout to be changing at every clock rising edge regardless of Din, you must use Moore FSM. When you use Mealy FSM, output depends on Din also. So everytime Din changes, FSM will check the current state and Dout will change accordingly. You can change testbench to make Din changing at the rising edge of the clock, it will work like what you want (Dout changes at rising edge). Below is the example testbench:

Code VHDL - [expand]
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clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 100 ns;
rst <= '0';
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
end process;



However, you have to see the fundamental of FSM machines as I said above.
 
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Armand86

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thanks for support, problem solved :)
 

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