problem with VHDL fsm

[FvM]

As far as I see, the internal oscillator is available through the STARTUP_XXX primitive, beginning with Virtex-5 and Spartan-6, not with any previous devices. Did I miss something?

 

[xtcx]

There is one PROM configuration clock for all FPGAs called CCLk I guess. Is it accessible to user design?, I mean can it be called for user clock functions?. Any idea?

 

[FvM]

I answered the question about accesibilty for Xilinx FPGA in my previous post.

 

[rreddy]

I would say use a synchronous state machine coded with a standard fsm template because it makes simulation, debugging, timing analysis and synthesis easier. This is what the EDA tools have been designed to handle.

 

[FvM]

I would say use a synchronous state machine.

The original poster already came to this conclusion, that brought up the discussion about oscillator options for a board, that hasn't been designed with a clock.

 

[rreddy]

Yeah, its unfortunate that the board design did not incorporate any clock. Its not common to see a completely clock-less logic device. Typically at least one of the external interfaces incorporates a clock.

Answering the original question; should there not be a sensitivity list that tells the process when to re-evaluate the process?

 

[FvM]

It should - just for consistent simulation. It's however ignored in synthesis.