Problem with VHDL entities in Quartus

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davorin

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VHDL entities in Quartus

Although I hate VHDL I have to use it from time to time (o;

And now I´m facing a strange problem with a altpll entity added in the top-level file.

Code: 
Info: Found 2 design units, including 1 entities, in source file clkpll.vhd
	Info: Found design unit 1: CLKPLL-SYN
	Info: Found entity 1: CLKPLL

It correctly sees the altpll module but later on it says that it is un defined:

Code: 
Error: VHDL error at usbtop.vhd(353): object "CLKPLL" is used but not declared
Error: Ignored construct USBTOP_arch at usbtop.vhd(35) because of previous errors


The top-level code looks like:

Code: 
u_PLL : CLKPLL 
port map (inclk0 => CLKINM, 
   pllena => '1',
   areset => RST, 
   c1 => GCLKM,
   c0 => CLKM, 
   locked => LOCK);


I know it must be something stupid...and I hate those stupid VHDL which requires the right order of files imported into Quartus *arrgggghh.
 

VHDL entities in qu@rtus

Hello davorin,

Is it possible that there is a problem with the names of entity, architecture and component? Do they match together? Some times ago I had a mistake in my code and I think the errors where the same. Is the file “clkpll.vhd“ from you?

Did you checked the order of the imported files in Quartus? That’s a very stupid thing as you said.

Bye,
cube007
 

Re: VHDL entities in Quartus

Yes..clkpll.vhd is generated with the wizard using "altpll"...
Entity and architecture names match and component is "altpll".


Hmm..and doesn't even work when use a verilog pll module..
 

VHDL entities in qu@rtus

You said that your component has the name altpll, that means that you instantiation should look like “u_PLL : altpll” and not “u_PLL : CLKPLL”. It is working like this in my case.
 

Re: VHDL entities in Quartus

Stupid (o;

Be careful using design files meant for Xilinx under Quartus (o;

Seems that Xilinx ISE doesn't require the "component" declaration for the PLL:

Code: 
component clkpll
	PORT
	(
		inclk0		: IN STD_LOGIC  := '0';
		areset		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;
		c1		: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC 
	);
end component;


Now works (o;
 

Re: VHDL entities in Quartus

Yes, that’s it. I created a project to check where the problem is. But you were faster than me (I had to help my mother with her PC :sm15: ). It is necessary to declare the component you would like to use in the architecture of usbtop.vhd.

Code: 
component clkpll
		port (
			inclk0	: IN STD_LOGIC;
			areset	: IN STD_LOGIC;
			c0		: OUT STD_LOGIC;
			c1		: OUT STD_LOGIC;
			locked	: OUT STD_LOGIC 
		);
	end component;
 

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