Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Library IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all;[CODE][/CODE] Entity calculator is Port ( clk : in std_logic; -- clock Clear, load, add : in std_logic; -- operation signals Din : in std_logic_vector (15 downto 0); -- input data Result : out std_logic_vector (15 downto 0)); -- output data End calculator Architecture a1 of calculator is Signal dReg : std_logic_vector (15 downto 0); Begin Process (clk) Begin If rising_edge (clk) then If clear =’1’ then dReg <= ”0000000000000000”; elsif load=’1’ then dReg <= din; elsif add=’1’ then dReg <= std_logic_vector(unsigned(dreg) + unsigned(din)); --values of dreg and din are converted to unsigned type with unsigned() function. --the unsigned values are added --the result is converted to standard logic vector with std_logic_vector() function. end if; end if; en process; result <= dreg; end a1;
What help do you need?
As you have not asked a question it is impossible to determine what you need help with, but don't expect someone to write the code for you.
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
Entity calculator is
Port ( clk : in std_logic; -- clock
Clear, load, add : in std_logic; -- operation signals
Din : in std_logic_vector (15 downto 0); -- input data
Result : out std_logic_vector (15 downto 0)); -- output data
End calculator;
Architecture a1 of calculator is
Signal dReg : std_logic_vector (15 downto 0);
Begin
Process (clk)
Begin
If (rising_edge (clk)) then
If (clear ='1') then
dReg <= ”"0000000000000000";
elsif (load='1') then
dReg <= Din;
elsif (add='1') then
dReg <= std_logic_vector(unsigned(dReg) + unsigned(Din));
--values of dreg and din are converted to unsigned type with unsigned() function.
--the unsigned values are added
--the result is converted to standard logic vector with std_logic_vector() function.
end if;
end if;
end Process;
Result <= dReg;
end a1;
It doesn't sound like you need a Q' output. The description indicates you need to do the following:
1.) add a "negate" input. it seems assumed that clear, negate, add, and load will be mutually exclusive.
2.) add an error bit that occurs when when an addition overflows. This can be done by making the result of the addition 17b. Making dReg into a 17b value has some additional complications, as you need to avoid setting the msb to 1 in the negate operation.
3.) have a nested if statement based on the error bit, preventing add, negate, and load from working until clear is used. "error" does not appear to be an output, although that would make more sense.
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
Entity calculator is
Port ( clk : in std_logic; -- clock
Clear, load, add, complement : in std_logic; -- operation signals
Din : in std_logic_vector (15 downto 0); -- input data
Result : out std_logic_vector (15 downto 0); -- output data
End calculator;
Architecture a1 of calculator is
Signal dReg : std_logic_vector (15 downto 0);
Begin
Process (clk)
Begin
If (rising_edge (clk)) then
If (clear ='1') then
dReg <= "0000000000000000";
elsif (load='1') then
dReg <= Din;
elsif (add='1') then
dReg <= std_logic_vector('0'& unsigned(dReg)+ unsigned(Din)); -- Using '0'& to be able to assign additional bit
case (dReg) is
when "1****************" => load <= '0';
when "1****************" => add <= '0';
when "1****************" => complement <= '0';
end case;
elsif (complement='1') then
dReg <= Din;
--values of dreg and din are converted to unsigned type with unsigned() function.
--the unsigned values are added
--the result is converted to standard logic vector with std_logic_vector() function.
end if;
end if;
end Process;
Result <= dReg;
end a1;
You missed the closing right parentheses at the end of the port list and there should be no terminating semi-colon at the end of the last entry in the port list. See below, changes in red fontHi
I made some changes on the code
The point is when compiling i have an error : near "End": expecting FUNCTION or PROCEDURE or IMPURE or PURECode:Entity calculator is Port ( clk : in std_logic; -- clock Clear, load, add, complement : in std_logic; -- operation signals Din : in std_logic_vector (15 downto 0); -- input data Result : out std_logic_vector (15 downto 0); -- output data End calculator;
Entity calculator is
Port ( clk : in std_logic; -- clock
Clear, load, add, complement : in std_logic; -- operation signals
Din : in std_logic_vector (15 downto 0); -- input data
Result : out std_logic_vector (15 downto 0)[B][COLOR=#FF0000]);[/COLOR][/B] -- output data
End calculator;
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
Entity calculator is
Port ( clk : in std_logic; -- clock
Clear, load, add, complement : in std_logic; -- operation signals
Din : in std_logic_vector (15 downto 0); -- input data
Erorr : in bit := 0; -- the erorr bit
Result : out std_logic_vector (15 downto 0)); -- output data
End calculator;
Architecture a1 of calculator is
Signal dReg : std_logic_vector (15 downto 0);
Begin
Process (clk)
Begin
If (rising_edge (clk)) then
If (clear ='1') then
dReg <= "0000000000000000";
elsif (load='1') then
dReg <= Din;
elsif (add='1') then
dReg <= std_logic_vector(Erorr & unsigned(dReg)+ unsigned(Din)); -- Using '0'& to be able to assign additional bit
case (Erorr) is
when '1' => Clear <= '1';
end case;
elsif (complement='1') then
dReg <= not Din;
--values of dreg and din are converted to unsigned type with unsigned() function.
--the unsigned values are added
--the result is converted to standard logic vector with std_logic_vector() function.
end if;
end if;
end Process;
Result <= dReg;
end a1;
Thanks a lot for your help
actually, what i am trying to do is to make the result of the sum is 17 bit, instead of 16 bit and when this last bit is '1', i want the circuit to stop working until performing clear again.
I made some changes
Code:Library IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all; Entity calculator is Port ( clk : in std_logic; -- clock Clear, load, add, complement : in std_logic; -- operation signals Din : in std_logic_vector (15 downto 0); -- input data Erorr : in bit := 0; -- the erorr bit Result : out std_logic_vector (15 downto 0)); -- output data End calculator; Architecture a1 of calculator is Signal dReg : std_logic_vector (15 downto 0); Begin Process (clk) Begin If (rising_edge (clk)) then If (clear ='1') then dReg <= "0000000000000000"; elsif (load='1') then dReg <= Din; elsif (add='1') then dReg <= std_logic_vector(Erorr & unsigned(dReg)+ unsigned(Din)); -- Using '0'& to be able to assign additional bit case (Erorr) is when '1' => Clear <= '1'; end case; elsif (complement='1') then dReg <= not Din; --values of dreg and din are converted to unsigned type with unsigned() function. --the unsigned values are added --the result is converted to standard logic vector with std_logic_vector() function. end if; end if; end Process; Result <= dReg; end a1;
any idea how to do that??
process (clk) is
begin
if rising_edge(clk) then
if clear = '1' then
-- dReg should be cleared
-- any error flag should be cleared.
elsif error_flag = '0' then
if load = '1' then
-- code for load
elsif add = '1' then
--code for the addition and to set the error_flag.
elsif complement = '1' then
-- code for complement
end if;
end if;
end if;
end process;
process (clk) is
begin
if rising_edge(clk) then
x <= a + b;
error_flag <= x(x'left); -- This adds +1 cycle of latency!
end if;
end process;
process (clk) is
begin
if rising_edge(clk) then
x <= a + b;
end if;
end process;
error_flag <= x(x'left); -- placed outside of process. can be annoying if process were long.
process (clk) is
variable result : unsigned(16 downto 0); -- variables can be tricky as the assignements happen _within_ the process vs at the end of the process.
begin
if rising_edge(clk) then
result := a + b; -- happens at this line.
x <= result(15 downto 0);
error_flag <= result(16);
end if;
end process;
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
Entity calculator is
Port ( clk : in std_logic; -- clock
Clear, load, add, complement : in std_logic; -- operation signals
Din : in std_logic_vector (15 downto 0); -- input data
Result : out std_logic_vector (15 downto 0)); -- output data
End calculator;
Architecture a1 of calculator is
Signal dReg : std_logic_vector (15 downto 0);
Begin
Process (clk)
Begin
If (rising_edge (clk)) then
If (clear ='1') then
dReg <= "0000000000000000";
elsif (load ='1') then
dReg <= Din;
elsif (add ='1') then
dReg <= std_logic_vector('0' & unsigned(dReg)+ unsigned(Din)); -- Using flag & to be able to assign additional bit
if (dReg(17) ='1') then
while (dReg(17)= '1') loop
dReg(17) <= '0' + dReg(17);
end loop;
elsif (clear ='1') then
dReg <= "0000000000000000";
end if;
elsif (complement='1') then
dReg <= not Din;
--values of dreg and din are converted to unsigned type with unsigned() function.
--the unsigned values are added
--the result is converted to standard logic vector with std_logic_vector() function.
end if;
end if;
end Process;
Result <= dReg;
end a1;
At least one error in the screenshot is more than clear its reason: The dReg signal is declared as being 16 bit size (15 downto 0), but you are attempting to access the 17th bit.
Thank you for you help, that gave me some good ideas, I made some changes and I think that is correct? is it?
Thanks in advance.
no, and in this case I'm having a hard time understanding the reasoning behind your changes.
You've added a while loop -- something that is exceptionally rare in synthesizable code. inside the while loop, you have dReg(17) -- a 1 bit scalar being assigned to '0' + dReg(17). This doesn't work for several reasons. First, dReg(17) doesn't exist as previously mentioned (it would also be the 18th bit). Second, "+" is not defined for two std_logic -- even in std_logic_unsigned this is not possible. Third, dReg <= '0' + dReg will only cause dReg to change at the end of the process -- this generates an infinite loop. Fourth, 0 + x = x, so even if the line were valid and took effect immediately, it wouldn't do anything.
In addition, you still don't have the nested if-else statements that I had suggested. (also you should attempt to post consistently indented code. It makes it easier on the reader.)
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
Entity calculator is
Port ( clk : in std_logic; -- clock
Clear, load, add, complement : in std_logic; -- operation signals
Din : in std_logic_vector (15 downto 0); -- input data
Result : out std_logic_vector (15 downto 0)); -- output data
End calculator;
Architecture a1 of calculator is
Signal dReg : std_logic_vector (15 downto 0);
Begin
Process (clk)
Begin
If (rising_edge (clk)) then
If (clear ='1') then
dReg <= "0000000000000000";
elsif (load ='1') then
dReg <= Din;
elsif (add ='1') then
dReg <= std_logic_vector('0' & unsigned(dReg)+ unsigned(Din)); -- Using flag & to be able to assign additional bit
if (dReg(16) ='1') then
while (dReg(16)= '1') loop
dReg(16 downto 16) <= ("0" + dReg(16 downto 16));
end loop;
elsif (clear ='1') then
dReg <= "0000000000000000";
end if;
elsif (complement='1') then
dReg <= not Din;
--values of dreg and din are converted to unsigned type with unsigned() function.
--the unsigned values are added
--the result is converted to standard logic vector with std_logic_vector() function.
end if;
end if;
end Process;
Result <= dReg;
end a1;
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?