Spartan II problem
What do you mean by, "my design fails"? The FPGA does not function as intended or the Xilinx tools fail to produce a bit file?
The Xilinx tools are optimizing your code. If you have lots of VHDL that does not have a valid IO pin as an input or does not ultimately drive an IO pin, the tools were remove this logic from the design. After you add the IO pin and recompile, the tools no longer strip out the logic and the design may no longer fit into the part.
Please provide info to exactly what stage of the build process fails and what error messages are given.
Are you storing servo settings in memory? Perhaps the design is running out of RAM blocks.