Problem with verilog file (regarding $readmemh)

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tanvirnsuer

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Hi,
I am trying to use $readmemh in verilog,but i am getting no error.
But, it displays xxxxxxxx value for input and output where I want hex numbers.

My code is as:
Code Verilog - [expand]
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module testbench;
 
    reg [31:0] a,b;
    reg [2:0] f;
    wire [31:0] y;
    wire zero;
  parameter vecs = 22; 
 
    alu alu0 (.a(a),.b(b),.f(f),.y(y),.zero(zero));
 
    reg [100:0] vec [0:vecs-1];
initial
$readmemh("C:\\Users\\Mac\\Desktop\\alu.txt",vec);
integer i;
initial
begin
for (i=0; i<vecs; i=i+1)
//{f,a,b,y,zero}=vec[i];
$display("f=%h, a=%h, b=%h,  y=%h, zero=%h",f, a, b, y, zero);
end
endmodule


this is the testbench for 32 bit ALU. My inputs are 32 bit a and b; f is my 3 bit select. Output is 32 bit y and 1 bit zero.
Zero=1 when output=0 and zero=0 when output=1.

In my program, I want that it will read the hex value from alu.txt and will display the result.
in my text file, the lines are as:
2_00000000_00000000_00000000_1
2_00000000_FFFFFFFF_FFFFFFFF_0
2_00000001_FFFFFFFF_00000000_1 etc; where 2 goes for select bit (here, add operation), next 8 bits are a, b and y respectively. The last one is zero bit.

Problem is whenever, I run the code it shows as:
f=x, a=xxxxxxxx, b=xxxxxxxx, y=xxxxxxxx, zero=x,
f=x, a=xxxxxxxx, b=xxxxxxxx, y=xxxxxxxx, zero=x,
..........................................................................
..........................................................................

Can you please help me to figure out the problem.
Thank you.

Best regards,
Tanvir
 

e: Problem with verilog file (regarding $readmemh)

I have changed a little bit in the $display line:

$display("f=%h, a=%h, b=%h, y=%h, zero=%h, vec=%h",f, a, b, y, zero, vec);

I have added vec to display.
now from the results window, i got the picture just like this:
**broken link removed**
I am not getting the value of anything except vec;
It should be as: the first 1 bit of vec is for f, second 8 bit for input a, third 8 bits of vec is for input b and then comes 8 bit output y and at the end 1 bit output for zero. [all the values are in hex]

So I am getting the values, but it works all together when I use vec.
How can I get the values separately for my inputs and outputs?

imbichie said:
I think we need to give the path of the file pointing from the current folder
like
Code: 
$readmemh("../alu.txt",vec);
etc note very sure, just try this
Click to expand...

Yes, tried this way.
but does not work.
Thanks.
 
Last edited:

You aren't using the data from $readmemh correctly..
Here is the corrected code:
Code Verilog - [expand]
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reg [31:0] a,b;
reg [2:0] f;
reg [31:0] y;
reg zero;
parameter vecs = 22; 
 
reg [103:0] vec [0:vecs-1];
 
integer i;
initial begin
  $readmemh("alu.txt",vec);
  for (i=0; i<vecs; i=i+1) begin
    {f,a,b,y,zero} = {vec[i][102:4],vec[i][0]};
    $display("f=%h, a=%h, b=%h,  y=%h, zero=%h",f, a, b, y, zero);
  end
end

For whatever reason you commented out the {f,a,b,y,zero} = vec; assignment, which was actually incorrect as each character is interpreted as a hex value. Therefore your vector 2_00000000_00000000_00000000_1 is 104-bits not 101-bits ([100:0]). The value for zero is in hex therefore you have to discard vec[3:1].
 

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