Problem with VCS_MX when simulating Verilog design with a SystemC module

[bjchen]

dear all: I am using vcs to simulate a verilog design contain a systemC module, when the vcs goes to the "using g++ for c++ compile" step, an error call "enviroment variable not found, may be vcs_mx is installed uncorrecttly."
but as I know, the verilog contain systemC simulation will not use VCS_MX, so is there anyone who has face the same problem as me, if yes, will you tell me what is the problem and tell the resolution, great thanks!