Problem with using while loop in VHDL

[jene2in]

Hi,

Is there any problem with using while loop at the start of the program in VHDL and Xilinx ISE. I keep getting parse error. The algorithm that I have will work best with While Loop and so I was wondering if anyone can point out anything with regards to while loop. Here's few lines frm my code:

begin
while (p(0) != 1) loop -- termination condition
--if p(0) = 0 then
if (a(1) = 0 and a(0) = 0) then -- A = 0 (mod 4)
a <= a srl 2; -- divide by 4
g0: MQRTR port map (w => u, m => m, f => u2); -- use MQRTR component
u <= u2;
if s = 0 then -- flag used to indicate the sign of delta
if d(2) = 0 then s <= 1;
end if;
if d(1) = 0 then
d <= d srl 2; -- divide D by 4
else
p <= p srl 1;
s <= 1;
end if;
else
d <= sll 2;
if p(1) <= 0 then
p <= p srl 2;
else
p <= p srl 1;
end if;
end if;

elsif a(0) = 0 then -- check if a is divisible by 2
a <= a srl 1;
g1: MHLV port map(c => u, m => m, d => u1 );
u <= u1;
if s = 0 then
if d(1) = 1 then
s <= 1;

 

[FvM]

While Loop

I can't see from the (rather long) snippet if the code would be synthesizable at all, I guess it isn't.

A frequent misunderstanding of iteration constructs in HDL code is, that they would create a sequential processing order as an iteration in a microprocessor program. But they don't!

They are a direction to generate parallel logic, one instance of the logic within the block for each iteration. To be synthesisable, the number of iterations must be finite and predictable for the HDL compiler. Otherwise the compiler would be stuck in an endless loop (resulting in a compilation error after reaching a predefined iteration limit).

In most cases, the only suitable solution is to code a really sequential program flow, using a clock.

 

[jene2in]

Re: While Loop

THANK YOU!!!

 

[nitin_ndg]

Re: While Loop

Y he is right