alext
Newbie level 6
ISE6.1 Bug ??
Hi All!
I got a problem using LUTs (any of them)in
schematic Design in ISE6.1. All signals connected to the Inputs of the LUTs are consedered as unused, so they are removed with LUTs connected to them. The reason of this seem to be wrong *vhf containing additional INIT statement. All this happening when I am using VHDL language in project property, in case of VERILOG all is OK. I'll be vary happy to know that I am wrong! I'll greatly appreciate any help to overcome this very annoing problem. Thanks in advance.
Hi All!
I got a problem using LUTs (any of them)in
schematic Design in ISE6.1. All signals connected to the Inputs of the LUTs are consedered as unused, so they are removed with LUTs connected to them. The reason of this seem to be wrong *vhf containing additional INIT statement. All this happening when I am using VHDL language in project property, in case of VERILOG all is OK. I'll be vary happy to know that I am wrong! I'll greatly appreciate any help to overcome this very annoing problem. Thanks in advance.