modelsim uninitialized value
Hi, folks,
Thank you for all your replies. Actually, the problem results from 'X'/'U' signal assignments, but the 'X'/'U' are not caused by improper initialization. it is all about the bi-directional signals.
I am designing a DDR2 memory controller. In the very top design, there is a port signal called DDR2_DQSp. It is a bidirectional data strobe signal shared by both READs and WRITEs.
This port signal is declared as follows:
DDR2_DQSp : inout std_logic_vector((DQS_WIDTH-1) downto 0);
In the testbench, this port signal is hooked up to the Micron Verilog Simulation Model. Inside the design, it was driven by signals as follows:
DDR2_DQSp <= ddr2_dqs_int;
the signal ddr2_dqs_int is driven by a bidirectional port signal from a sub-component(one hierarchy level below the very top design). After watching the waveform, I found out that DDR2_DQSp becomes 'x'.....
Then, I hooked up DDR2_DQSp directly to the bidirectional port signal in the sub-component, the problem is gone.
In summary, the bidirectional port signals have to be dealt with properly; otherwise, modelsim will drive it to 'X'
Thank you