I presume you don't expect anybody to explain the meaning of this arbitrary code snippet.
'0' & cycle_wait(cycle_wait'high downto 1) is a concatenation operation, a usual way to combine bits and bit vector selections to a new bit vector.
In this case it's setting the leftmost bit to zero and copying all except the rightmost bit of cyccle_wait to the result. In other words, it's a logical right shift.
I presume you don't expect anybody to explain the meaning of this arbitrary code snippet.
'0' & cycle_wait(cycle_wait'high downto 1) is a concatenation operation, a usual way to combine bits and bit vector selections to a new bit vector.
In this case it's setting the leftmost bit to zero and copying all except the rightmost bit of cyccle_wait to the result. In other words, it's a logical right shift.