Problem with UART. Need to test UART with variable baud rate on altera de2 115 board

[satty_008]

Problem with UART code in VHDL... Please Help

process (rst, clk, cycle_wait)
variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
begin
if rst = '1' then
wait_clk_cycles := (others => '0');
half_cycle := '0' & cycle_wait(cycle_wait'high downto 1);
genTick <= '0';

Can anyone please explain the highlighted line.


Also what is meant by oversampling with refrence to UART?

 

[FvM]

I presume you don't expect anybody to explain the meaning of this arbitrary code snippet.

'0' & cycle_wait(cycle_wait'high downto 1) is a concatenation operation, a usual way to combine bits and bit vector selections to a new bit vector.

In this case it's setting the leftmost bit to zero and copying all except the rightmost bit of cyccle_wait to the result. In other words, it's a logical right shift.

 

[satty_008]

I presume you don't expect anybody to explain the meaning of this arbitrary code snippet.

'0' & cycle_wait(cycle_wait'high downto 1) is a concatenation operation, a usual way to combine bits and bit vector selections to a new bit vector.

In this case it's setting the leftmost bit to zero and copying all except the rightmost bit of cyccle_wait to the result. In other words, it's a logical right shift.

Thank you... That was helpful..

could you also please tell me what is meant by oversampling ?