library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
port(
clk : in std_logic;
HS,VS,VGACLK : out std_logic;
R,G,B : out std_logic_vector(7 downto 0));
end fifo;
architecture main of fifo is
-----------signals----------------------
signal clk_49,clk_143 : std_logic;
signal datain, dataout : std_logic_vector(7 downto 0);
signal addr2,addr1 : integer range 0 to 2047 := 0;
signal hpos,vpos : integer range 0 to 2047 := 0;
---------------------------------------------------
component pll is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
clk_49_clk : out std_logic; -- clk
clk_143_clk : out std_logic -- clk
);
end component pll;
component simple_dual_port_ram_dual_clock is
port
(
rclk : in std_logic;
wclk : in std_logic;
raddr : in natural range 0 to 2047;
waddr : in natural range 0 to 2047;
data : in std_logic_vector(7 downto 0);
we : in std_logic := '1';
q : out std_logic_vector(7 downto 0)
);
end component simple_dual_port_ram_dual_clock;
component sync is
port(
clk : in std_logic;
data : in std_logic_vector(7 downto 0);
hsync, vsync: out std_logic;
R,G,B : out std_logic_vector(7 downto 0)
);
end component sync;
begin
VGACLK <= clk_49;
u2 : component sync
port map (clk_49,dataout,HS,VS,R,G,B);
u0 : component pll
port map (
clk_clk => clk, -- clk.clk
reset_reset_n => '1', -- reset.reset_n
clk_49_clk => clk_49, -- clk_49.clk
clk_143_clk => clk_143 -- clk_143.clk
);
u1 : component simple_dual_port_ram_dual_clock
port map (clk_143,clk_49,addr2,addr1,datain,'1',dataout);
process(clk_143)
begin
if(clk'event and clk='1') then
-------loop-----------------
if(hpos<1055)then
hpos<=hpos+1;
else
hpos<=0;
if(vpos<625)then
vpos<=vpos+1;
else
vpos<=0;
end if;
end if;
------------------------------
if (addr1 = addr2) then
------do nothing-------------
else
if(hpos = 600 or vpos = 300) then
datain<= (others=> '1');
else
datain<= (others=> '0');
end if;
addr1 <= addr1 + 1;
if(addr1 = 1055)then
addr1<=0;
end if;
end if;
end if;
end process;
process(clk_49)
begin
if(clk'event and clk='1') then
addr2 <= addr2 + 1;
if(addr2 = 1055)then
addr2<=0;
end if;
end if;
end process;
end main;