Hello , i'm working now in project to extend an IP Core and i should implement a 16 bit counter with 12 MHz
the problem i did all the simulations (Back annotation also) and it gives me the right timing . unfortunately when we transfer the program
the time changed and it gives less than the expected time. any help
thanks in Advance
A 16 bit counter at 12MHz shouldn't give a problem with any FPGA (even if designad as async counter).
If simulation works, then I assume it is a " real world" problem:
--> Check power at all supply pins, are all power supply capacitors installed, correct capacitor type, short wiring,
--> Check input clock, ringing on external (clock) signal lines, correct signal levels, correct IO setup...