# problem with the counter

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#### QMA

##### Member level 4
dear all
I have designed following code in verilog using Xilinx and it is not giving me the results. i have a 16 bit vector bit_s_row. i want to calculate 1's from index i = 0 up to the index B_addr. Please help me in resolving the issue.
Code:
   if(i<B_addr)
begin
if(bits_s_row[i]==1)
pop_count = pop_count +1'b1;
else
pop_count = pop_count;
i=i+1;
end

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#### aminpix

##### Member level 3
You should'n't use IF command. may be you wanted to type FOR instead, but I am not sure in real implemention you can have for or not.
if it is only for simulation, instead of the first IF use "FOR":
Code:
for (i = 0; i < B_addr; i = i +1)
begin
if(bits_s_row[i]==1)
pop_count = pop_count +1'b1;
else
pop_count = pop_count;
i=i+1;
end

Last edited by a moderator:

#### aruipksni

##### Full Member level 6
your code is to ambigious for hdl design.
you dont know what the syntisizer will make out of it.

for wloop orks in hdl only on constant range value.

to implement this you will need to do for on full range - 16.

the basic idea is to code or convert indexes to numbers.
for example bits_s_row will now have 4 extra bits indicate index number

so to do everthing in parallel
you will need 16 comperators to compare index number to b_addr.
this will give you a masking bit vector.
and then you will need to sum all this numbers - depends how you do sum.

QMA

Points: 2