problem with substrate connection in cadence

[mrzargar]

Hello,

I am using a single schematic for three separate circuits in cadence IC615. When I use same contacts for substrate of my NMOS transistors I get an incorrect AC response. However, my transfer characteristics in noise analysis of cadence looks fine. I would really appreciate that if someone can help me with my problem.

Thank you

 

[nature0303]

Hi,
If your circuit is on P-sub,then all the substrate port of NMOS should be connected to GND to decrease the bias current between P-sub and N-Well,and since Pmos is set in N-well,mostly the substrate port can connected to Vdd,and the can also be connected to source of PMOS to eliminate the effect of substrate bias effect.Is that clear to you?