Problem with sampling storage for big datastreams in DSO

[renner_2004]

DSO again

hi,

i want to design a dso relate more or less to Johann glaser (http://www.johann-glaser.at/projects/DSO/) variant. The maximum sampling frequence should be 100MHz. Per channel i want to have 512kByte sampling storage.
My problem is the sampling storage for this big datastream. I think ZBT Sram are the best solution but they are very expensive and not easy to get.
Here are my questions:
-are SDRAM or DDRAM a better solution, can they process such big datastreams?
- if so, are there any vhdl solutions similar to my problem (i forgot: i want to use a spartan3 fpga)

 

[eda4you]

Re: DSO again

hi,

maybe i can give you another design idea. Try to use 2 or more parallel data paths to storage data --> each time interleaved. For instance data path 1 storage one data during two cylcles while in data path 2 the next data is storaged during the next 2 cycle. this can be done by simple logic. So you can reduce the max. writing cylce and can use simple and cheap memories.

 

[renner_2004]

Re: DSO again

thank you,

could be a solution. But i will need a fpga device with much more pins ( BGA :-( ). By the way, does anybody know how to solder a BGA device?