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problem with pspice transient simulation

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rajrevanth61

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Hello,
i have a circuit for a CLB in FPGA. I am getting convergence problem with the transient simulation.


Here is the output file.

Please help


Code: 
**** 06/18/14 11:46:38 ****** PSpice 16.5.0 (April 2011) ****** ID# 0 ********

 *clb*


 ****     CIRCUIT DESCRIPTION


******************************************************************************



*decoder*
*logic gate subcircuit for NAND 
.subckt NAND A B Y
sw1 vdd  Y  A vdd smod1
sw2 vdd  Y  B vdd smod1
sw3 Y 1 A 0 smod2
sw4 1  0 B  0 smod2
vdd vdd 0 dc 1 
.ends

*logic gate subcircuit for NOT
.subckt NOT in out 
sw5 vdd  out in vdd smod1
sw6 out 0 in  0 smod2 
vdd vdd 0 dc 1
.ends

*inputs
vA0 A0 0 0
vA1 A1 0 0

*calling NOT subcircuit
XNOT1 A0 YA0 NOT
XNOT2 A1 YA1 NOT

*calling nand subcircuits
XNAND1 YA0 YA1 bl NAND
XNAND2 A0  YA1 bl1 NAND
XNAND3 YA0 A1  bl2 NAND
XNAND4 A0  A1  bl3 NAND


*sram*
*source
vdd vdd 0 dc 1

*data control
*vbl bl 0 dc 1
vblb blb 0 dc 0  

*access control
vwl wl 0 pulse(0 2 4m 100u 100u 5m 6m)

*transistors used for latching
sw7 QR 0 Q  0 smod2

sw8 QR vdd Q vdd smod1

sw9 Q 0 QR  0 smod2

sw10 Q vdd QR vdd smod1


*transistors used for data access
sw11 bl Q wl  0 smod2
sw12 blb  QR wl 0 smod2

*sram2*



*data control
*vbl bl1 0 dc 1
vblb1 blb1 0 dc 1 

*access control
vwl1 wl1 0 pulse(0 2 4m 100u 100u 5m 6m)

*transistors used for latching
sw13 QR1 0 Q1  0 smod2

sw14 QR1 vdd Q1 vdd smod1

sw15 Q1 0 QR1  0 smod2

sw16 Q1 vdd QR1 vdd smod1


*transistors used for data access
sw17 bl1 Q1 wl1 0 smod2
sw18 blb1 QR1 wl1 0 smod2

*sram3*

*data control
*vbl bl2 0 dc 1
vblb2 blb2 0 dc 1

*access control
vwl2 wl2 0 pulse(0 2 4m 100u 100u 5m 6m)

*transistors used for latching
sw50 QR2 0 Q2  0 smod2

sw19 QR2 vdd Q2 vdd smod1

sw20 Q2 0 QR2  0 smod2

sw21 Q2 vdd QR2 vdd smod1


*transistors used for data access
sw22 bl2  Q2 wl2 0 smod2
sw23 blb2 QR2 wl2 0 smod2


*sram4*

*data control
*vbl bl 0 dc 1
vblb3 blb3 0 dc 1

*access control
vwl3 wl3 0 pulse(0 2 4m 100u 100u 5m 6m)

*transistors used for latching
sw24 QR3 0 Q3  0 smod2

sw25 QR3 vdd Q3  vdd smod1

sw26 Q3 0 QR3  0 smod2

sw27 Q3 vdd QR3 vdd smod1


*transistors used for data access
sw28 bl3 Q3 wl3 0 smod2
sw29 blb3 QR3 wl3  0 smod2

*4x1 Multiplexer
*logic gate subcircuit for AND
.subckt AND A B C Y
sw30 vdd  Y0 A vdd smod1
sw31 vdd  Y0 B vdd smod1
sw32 vdd  Y0 C vdd smod1

sw33 Y0 1 A  0 smod2
sw34 1 2 B  0 smod2
sw35 2 0 C  0 smod2

sw36 vdd Y Y0  vdd smod1
sw37 Y   0 Y0  0   smod2
vdd vdd 0 dc 1 
.ends


*logic gate subcircuit for NOT1
.subckt NOT1 in out 
sw38 vdd  out in vdd smod1
sw39 out 0 in  0 smod2 
vdd vdd 0 dc 1
.ends


*logic gate subcircuit for OR
.subckt OR A B C D Y 
sw40 vdd 1 A  vdd smod1
sw41 1   2 B  vdd smod1
sw42 2   3 C  vdd smod1
sw43 3   Y0 D  vdd smod1

sw44 Y0 0 A  0 smod2
sw45 Y0 0 B  0 smod2
sw46 Y0 0 C  0 smod2
sw47 Y0 0 D  0 smod2

sw48  vdd Y Y0  vdd  smod1
sw49 Y   0 Y0 0    smod2
vdd vdd 0 dc 1
.ends

vS0 S0 0 0
vS1 S1 0 0 
*calling NOT subcircuit
XNOT11 S0 YA01 NOT
XNOT12 S1 YA11 NOT


*vA A 0 0
*vB B 0 1
*vC C 0 1
*vD D 0 1

*calling and subcircuits
XAND1  Q  YA11 YA01 Y0M AND
XAND2  Q1 YA11 S0  Y1M AND
XAND3  Q2 S1  YA01 Y2M AND
XAND4  Q3 S1  S0  Y3M AND

*calling or subcircuit
XOR1  Y0M Y1M Y2M Y3M R OR




.tran 10m 100m uic 

.probe


.MODEL Smod1 VSWITCH(Ron=1000 Roff=1 Von=1V Voff=0.5V)
.MODEL Smod2 VSWITCH(Ron=1 Roff=1000 Von=1V Voff=0.5V)

 .end

**** 06/18/14 11:46:38 ****** PSpice 16.5.0 (April 2011) ****** ID# 0 ********

 *clb*


 ****     Voltage Controlled Switch MODEL PARAMETERS


******************************************************************************




               smod1           smod2           
         RON    1.000000E+03    1            
        ROFF    1               1.000000E+03 
         VON    1               1            
        VOFF     .5              .5          

Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.

ERROR(ORPSIM-15138): Convergence problem in transient analysis at Time =  4.041E-03.
         Time step =  17.79E-21, minimum allowable step size =  1.000E-18

  These voltages failed to converge:

    V(XAND1.1)                =    42.37mV  \    42.73mV
    V(XAND1.2)                =    21.18mV  \    21.37mV

ERROR(ORPSIM-15659): Discontinuing simulation due to convergence problem



  Last node voltages tried were:

 NODE   VOLTAGE     NODE   VOLTAGE     NODE   VOLTAGE     NODE   VOLTAGE


(    Q)     .7331  (    R)     .5050  (   A0)    0.0000  (   A1)    0.0000      

(   bl)     .7971  (   Q1)     .8448  (   Q2)     .8448  (   Q3)     .8448      

(   QR)     .8813  (   S0)    0.0000  (   S1)    0.0000  (   wl)     .8125      

(  bl1)     .9913  (  bl2)     .9913  (  bl3)     .9915  (  blb)    0.0000      

(  QR1)     .8442  (  QR2)     .8442  (  QR3)     .8442  (  vdd)    1.0000      

(  wl1)     .8125  (  wl2)     .8125  (  wl3)     .8125  (  Y0M)     .5010      

(  Y1M)     .5000  (  Y2M)     .5000  (  Y3M)     .5000  (  YA0)     .9990      

(  YA1)     .9990  ( blb1)    1.0000  ( blb2)    1.0000  ( blb3)    1.0000      

( YA01)     .9990  ( YA11)     .9990  (XOR1.1)     .9961 (XOR1.2)     .9921     

(XOR1.3)     .9882 (XAND1.1)     .0424                   (XAND1.2)     .0212    

(XAND2.1)     .9948                   (XAND2.2)     .9938                       

(XAND3.1)     .9948                   (XAND3.2) 993.9E-06                       

(XAND4.1)     .9974                   (XAND4.2)     .4987                       

(XOR1.Y0)     .9843                   (XAND1.Y0)     .9929                      

(XAND2.Y0)     .9997                  (XAND3.Y0)     .9997                      

(XAND4.Y0)     .9998                  (XNAND1.1)     .3986                      

(XNAND2.1) 990.4E-06                  (XNAND3.1)     .9903                      

(XNAND4.1)     .4958                  (XOR1.vdd)    1.0000                      

(XAND1.vdd)    1.0000                 (XAND2.vdd)    1.0000                     

(XAND3.vdd)    1.0000                 (XAND4.vdd)    1.0000                     

(XNOT1.vdd)    1.0000                 (XNOT2.vdd)    1.0000                     

(XNAND1.vdd)    1.0000                (XNAND2.vdd)    1.0000                    

(XNAND3.vdd)    1.0000                (XNAND4.vdd)    1.0000                    

(XNOT11.vdd)    1.0000                (XNOT12.vdd)    1.0000                


**** Interrupt ****
**** Param: RELTOL = 0.001
**** Param: ABSTOL = 1e-012
**** Param: VNTOL = 1e-006
**** Param: GMIN = 1e-012
**** Param: TSTOP = 0.1
**** Param: TMAX = 0
**** Param: ITL1 = 150
**** Param: ITL2 = 20
**** Param: ITL4 = 10
**** Param: RELTOL = 0.001
**** Param: ABSTOL = 1e-012
**** Param: VNTOL = 1e-006
**** Param: GMIN = 1e-012
**** Param: TSTOP = 0.1
**** Param: TMAX = 0
**** Param: ITL1 = 150
**** Param: ITL2 = 20
**** Param: ITL4 = 10

 **** Published Runtime Parameters *****************************
                                                               
                                       ABSTOL =      1.0000E-12
                                         GMIN =      1.0000E-12
                                         ITL1 =      1.5000E+02
                                         ITL2 =      2.0000E+01
                                         ITL4 =      1.0000E+01
                                       RELTOL =      1.0000E-03
                                       RUNFOR =      0.0000E+00
                                         TMAX =      0.0000E+00
                                        TSTOP =      1.0000E-01
                                       vA0.ac =      0.0000E+00
                                  vA0.acphase =      0.0000E+00
                                       vA0.dc =      0.0000E+00
                                       vA1.ac =      0.0000E+00
                                  vA1.acphase =      0.0000E+00
                                       vA1.dc =      0.0000E+00
                                      vblb.ac =      0.0000E+00
                                 vblb.acphase =      0.0000E+00
                                      vblb.dc =      0.0000E+00
                                     vblb1.ac =      0.0000E+00
                                vblb1.acphase =      0.0000E+00
                                     vblb1.dc =      1.0000E+00
                                     vblb2.ac =      0.0000E+00
                                vblb2.acphase =      0.0000E+00
                                     vblb2.dc =      1.0000E+00
                                     vblb3.ac =      0.0000E+00
                                vblb3.acphase =      0.0000E+00
                                     vblb3.dc =      1.0000E+00
                                       vdd.ac =      0.0000E+00
                                  vdd.acphase =      0.0000E+00
                                       vdd.dc =      1.0000E+00
                                        VNTOL =      1.0000E-06
                                       vS0.ac =      0.0000E+00
                                  vS0.acphase =      0.0000E+00
                                       vS0.dc =      0.0000E+00
                                       vS1.ac =      0.0000E+00
                                  vS1.acphase =      0.0000E+00
                                       vS1.dc =      0.0000E+00
                                       vwl.ac =      0.0000E+00
                                  vwl.acphase =      0.0000E+00
                                       vwl.dc =      0.0000E+00
                                      vwl1.ac =      0.0000E+00
                                 vwl1.acphase =      0.0000E+00
                                      vwl1.dc =      0.0000E+00
                                      vwl2.ac =      0.0000E+00
                                 vwl2.acphase =      0.0000E+00
                                      vwl2.dc =      0.0000E+00
                                      vwl3.ac =      0.0000E+00
                                 vwl3.acphase =      0.0000E+00
                                      vwl3.dc =      0.0000E+00
                                 XAND1.vdd.ac =      0.0000E+00
                            XAND1.vdd.acphase =      0.0000E+00
                                 XAND1.vdd.dc =      1.0000E+00
                                 XAND2.vdd.ac =      0.0000E+00
                            XAND2.vdd.acphase =      0.0000E+00
                                 XAND2.vdd.dc =      1.0000E+00
                                 XAND3.vdd.ac =      0.0000E+00
                            XAND3.vdd.acphase =      0.0000E+00
                                 XAND3.vdd.dc =      1.0000E+00
                                 XAND4.vdd.ac =      0.0000E+00
                            XAND4.vdd.acphase =      0.0000E+00
                                 XAND4.vdd.dc =      1.0000E+00
                                XNAND1.vdd.ac =      0.0000E+00
                           XNAND1.vdd.acphase =      0.0000E+00
                                XNAND1.vdd.dc =      1.0000E+00
                                XNAND2.vdd.ac =      0.0000E+00
                           XNAND2.vdd.acphase =      0.0000E+00
                                XNAND2.vdd.dc =      1.0000E+00
                                XNAND3.vdd.ac =      0.0000E+00
                           XNAND3.vdd.acphase =      0.0000E+00
                                XNAND3.vdd.dc =      1.0000E+00
                                XNAND4.vdd.ac =      0.0000E+00
                           XNAND4.vdd.acphase =      0.0000E+00
                                XNAND4.vdd.dc =      1.0000E+00
                                 XNOT1.vdd.ac =      0.0000E+00
                            XNOT1.vdd.acphase =      0.0000E+00
                                 XNOT1.vdd.dc =      1.0000E+00
                                XNOT11.vdd.ac =      0.0000E+00
                           XNOT11.vdd.acphase =      0.0000E+00
                                XNOT11.vdd.dc =      1.0000E+00
                                XNOT12.vdd.ac =      0.0000E+00
                           XNOT12.vdd.acphase =      0.0000E+00
                                XNOT12.vdd.dc =      1.0000E+00
                                 XNOT2.vdd.ac =      0.0000E+00
                            XNOT2.vdd.acphase =      0.0000E+00
                                 XNOT2.vdd.dc =      1.0000E+00
                                  XOR1.vdd.ac =      0.0000E+00
                             XOR1.vdd.acphase =      0.0000E+00
                                  XOR1.vdd.dc =      1.0000E+00
                                               
               

ERROR(ORPSIM-15138): Convergence problem in transient analysis at Time =  4.041E-03.
         Time step =  142.3E-21, minimum allowable step size =  1.000E-18

  These voltages failed to converge:

    V(XAND1.1)                =    42.37mV  \    42.73mV
    V(XAND1.2)                =    21.18mV  \    21.37mV

ERROR(ORPSIM-15659): Discontinuing simulation due to convergence problem



  Last node voltages tried were:

 NODE   VOLTAGE     NODE   VOLTAGE     NODE   VOLTAGE     NODE   VOLTAGE


(    Q)     .7331  (    R)     .5050  (   A0)    0.0000  (   A1)    0.0000      

(   bl)     .7971  (   Q1)     .8448  (   Q2)     .8448  (   Q3)     .8448      

(   QR)     .8813  (   S0)    0.0000  (   S1)    0.0000  (   wl)     .8125      

(  bl1)     .9913  (  bl2)     .9913  (  bl3)     .9915  (  blb)    0.0000      

(  QR1)     .8442  (  QR2)     .8442  (  QR3)     .8442  (  vdd)    1.0000      

(  wl1)     .8125  (  wl2)     .8125  (  wl3)     .8125  (  Y0M)     .5010      

(  Y1M)     .5000  (  Y2M)     .5000  (  Y3M)     .5000  (  YA0)     .9990      

(  YA1)     .9990  ( blb1)    1.0000  ( blb2)    1.0000  ( blb3)    1.0000      

( YA01)     .9990  ( YA11)     .9990  (XOR1.1)     .9961 (XOR1.2)     .9921     

(XOR1.3)     .9882 (XAND1.1)     .0424                   (XAND1.2)     .0212    

(XAND2.1)     .9948                   (XAND2.2)     .9938                       

(XAND3.1)     .9948                   (XAND3.2) 993.9E-06                       

(XAND4.1)     .9974                   (XAND4.2)     .4987                       

(XOR1.Y0)     .9843                   (XAND1.Y0)     .9929                      

(XAND2.Y0)     .9997                  (XAND3.Y0)     .9997                      

(XAND4.Y0)     .9998                  (XNAND1.1)     .3986                      

(XNAND2.1) 990.4E-06                  (XNAND3.1)     .9903                      

(XNAND4.1)     .4958                  (XOR1.vdd)    1.0000                      

(XAND1.vdd)    1.0000                 (XAND2.vdd)    1.0000                     

(XAND3.vdd)    1.0000                 (XAND4.vdd)    1.0000                     

(XNOT1.vdd)    1.0000                 (XNOT2.vdd)    1.0000                     

(XNAND1.vdd)    1.0000                (XNAND2.vdd)    1.0000                    

(XNAND3.vdd)    1.0000                (XNAND4.vdd)    1.0000                    

(XNOT11.vdd)    1.0000                (XNOT12.vdd)    1.0000                


**** Interrupt ****
 
Last edited by a moderator:

All your so called "transistors" (SPICE switch elements) have infinite bandwidth. You should add realistic node capacitance. Otherwise you can perform a purely digital simulation with less resource effort.
 

FvM said:
All your so called "transistors" (SPICE switch elements) have infinite bandwidth. You should add realistic node capacitance. Otherwise you can perform a purely digital simulation with less resource effort.
Click to expand...

what does purely digital simulation mean?
 

Review chapter "digital devices" in PSpice reference manual. Only available with PSpice AD (mixed mode simulation option).
 

I tried you ckt with ITL4=100. It simulates successfully.
I used pspice versiion 16.6 though.
 
mvaseem said:
I tried you ckt with ITL4=100. It simulates successfully.
I used pspice versiion 16.6 though.
Click to expand...

Can I know like what is ITL4=100?

- - - Updated - - -

I got to know what is ITL4=100 .
Even i tried changing it in the runtime settings but it is showing the same error as earlier, even Iam using 16.6 version only
 

I am attaching the circuit file I tried. Change the extension from .txt -> .cir .
This runs successfully at my end.
 

Attachments

  • forum_1.txt
    3.4 KB · Views: 78
Looks like I forgot to add following in the file -

.options ITL4=100.

Don't change run-time settings. Provide the above option through simulation settings and run simulation.
 
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