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problem with pll lock during ATPG simulations

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Apr 6, 2010
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Hyderabad, India
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I my design pll is taking a amount of 20Kns to get locked. Due to this i am getting errors during ATPG simulations. Is there any way to say the tool to wait untill this period.
Can some one help me regarding this.

do you need to have the pll lock to done your generate your stuck patterns?
I beleived not, and you could ignore this lock info from your pll during the stuck pattern generation, and the patterns will be independent of this value.
hi rca,
I am getting the clock with required frequency only after the pll is locked. Then how to say to the tool to perform simulations only after pll is locked.I tried to keep this delay value in the verilog pattern file and able to pass the simulations. But as we deliver the STIL patterns how to give this info.

Help me please.

for clarification, do you need to used the clock generated by the PLL to run your scan patterns?

hi rca,
I am running atpg simulations for the patterns those are generated by pll. During ATPG i blackboxed the pll and during simulations i am using behaviour model and able to produce the required clock.Using this clock for running simulations.

how do you expect the tester can synchronize the clock from the pll with the pattern?

Unless the pll is locked we cannot get the required clock right? As i am during atspeed pll simulations i need to push the patterns only when the pll produces the required clock. Then some how we need to say the tool to wait untill this period right?

Define the PLL Initialization in spf so that pll lock happens before ATPG starts in your patterns.

As rca suggested, you dont need PLL to be active in ATPG stuck at tests.
You can configure the PLL in bypass mode for stuck at and drive all clocks externally from ATE.
If your tester cant generate the double pulsing at required rate, for transition patterns you can use the PLL.

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