Hi all,
I'm designing a module in Verilog and need to use some parameters. For example, I have two parameters: 'a' and 'b' and the value of 'b' depend on 'a'. I use the folow code but It had not run yet.
Code:
localparam a = 9, b = 10;
initial
if (a = 1) b = 2;
else if (a =2) b = 3;
Which verilog statement is suitable for this case?