mpeg2 vhdl
Technical:
Given the amount of Multipliers in an MPEG2 decoder, you should think of maybe increasing the Clock speed by a factor of 3 (120Mhz - if that is impossible maybe to 80Mhz) - and reusing Multipliers (thus reducing the Multipliers Gate area by a factor of 3, or 2 respectively). Also check if it is possible to reduce the bit word-length of a Multiplier input Arguments. Also - have you optimized your Multipliers - there's whole theory (Booth...etc...) about how to do it.
Market:
The above notes by 'rntsay' are correct. Moreover, the main market for MPEG2 HW decoder chips (at least nowadays) - are DVD Players - where companies like Zoran are making buckets of Bucks ($$M) from.
Maybe an MPEG4 ASIC for next generation compression (DivX, etc) is a feasible market.
And, of course, the other main market, is a SW MPEG2 decoder, used mainly on PCs....