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Problem with MPEG2 videodecoder and ASIC/FPGA gates

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Newbie level 6
Jul 18, 2002
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mpeg decoder vhdl

I am a newbie and I need some help now. I would be glad if somedbody could help me. About one year ago I have read something about chip design and about hardware descrition languages. I found this topic very interesting. Then I had the idea of coding a MPEG2 videodecoder in VHDL for an FPGA. I found an commercial MPEG videodecoder IP core on which took about 50000 gates in an ASIC @ about 40 Mhz. Then I found these Spartan II FPGAs from Xilinx which had up to 300 000 system gates. I thought great! A videodecoder with 50000 system gates would fit into the FPGA and a VHDL Sparc CPU from too which took about 30000 system gates as ASIC design. Then I began to write a software model for the MPEG1/2 videodecoder in C which I wanted to translate after that into hardware. Some months ago I have completed the software decoder and it worked well. I have started to write an iDCT core and a SDRAM controller in VHDL. But then I had a bad surprise:(
I compiled the iDCT core with the Xilinx Webpack software and it didn't even fit into an 200 000 gate FPGA. OK, perhaps it was a little bit bad described but normally this couldn't be. Then I compiled an Z80 CPU and it took about 50 % of an 200 000 gate Spartan II. As ASIC it has about 8000 gates. This is 10 times so much as I have expected! Then I read the synthesis results of the Sparc CPU from Jiri Gaisler and it was the same with it. Also 10 times so much gates in an Virtex FPGA. Now I have realized that I can't compare ASIC gates with these "FPGA gates". The indications for these Xilinx FPGAs are idiotic! :evil:

So my MPEG videodecoder would never fit into an 300k gate FPGA. And now I have the problem that I don't know what I should do now. Perhaps the decoder would fit into a Virtex FPGA but they are so expensive and manufactoring an ASIC is also very expensive. Has anyone a hint for me?

vhdl mpeg

you (re)discovered the conversion factor 1 asic "gate" = 8-10 fpga "gate";
there's nothing you can do about that. if your design has a lot of multipliers, you can get the newer fpga with built-in hardcoded multipliers;
this helps, but for random logic the situation is the same.

as far as silicon area, asic will always be a lot smaller and cheaper to make than fpga, but the manufacture cost is huge, so it only makes sense if you think you will sell a lot of chips (100,000+) and if you have a lot of money (at least a few hunder thousand us $).

if you're trying to make some money out of your design, try to prefect it and validate it; you might be able to sell it as IP to a big company.
mpeg-2 is also relatively old; a lot of companies have existing asics that
can do it. something newer and less available is easier to sell.

mpeg2 vhdl

Given the amount of Multipliers in an MPEG2 decoder, you should think of maybe increasing the Clock speed by a factor of 3 (120Mhz - if that is impossible maybe to 80Mhz) - and reusing Multipliers (thus reducing the Multipliers Gate area by a factor of 3, or 2 respectively). Also check if it is possible to reduce the bit word-length of a Multiplier input Arguments. Also - have you optimized your Multipliers - there's whole theory (Booth...etc...) about how to do it.

The above notes by 'rntsay' are correct. Moreover, the main market for MPEG2 HW decoder chips (at least nowadays) - are DVD Players - where companies like Zoran are making buckets of Bucks ($$M) from.
Maybe an MPEG4 ASIC for next generation compression (DivX, etc) is a feasible market.
And, of course, the other main market, is a SW MPEG2 decoder, used mainly on PCs....

mpeg 2 decoder vhdl

FPGA is not a good candidate for MPEG2 decoder, not efficient, too expensive

fpga mpeg2

FPGA is not a good candidate for MPEG2 decoder, not efficient, too expensive

vhdl mpeg decoder

Whatch out for the new 'low cost' Virtex 2 devices (spartan 3?). They will probably have hardware multipliers available and will be somewhat bigger. You'll have to wait until they're commercially available though! I hope Q2-Q3 2003 :roll:

vhdl mpeg encoder

It is verification only to design MPEG2 decoder to use FPGA.
Verify function to use FPGA and actuality chip need method that embody using ASIC.

mpeg2 vhdl implementation

Hi TVMaster,
Share your MPEG4 IP please.

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