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Problem with Modelsim Simulation

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cherukukeshav

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vsim-3043

Hi

I used Flipflop primitive from language templates of Xilinx ISE9.1i in my design.

Problem-
When i try to simulate the design using modelsim. iam getting error like this..

project open {C:/Documents and Settings/keshago/Desktop/tetbench/flop}
# Loading project flop
# Compile of tesflop.v was successful.
vsim -L {C:/Documents and Settings/keshago/Desktop/resource/parts_lib} work.tesflop_v
# vsim -L {C:/Documents and Settings/keshago/Desktop/resource/parts_lib} work.tesflop_v
# Loading work.tesflop_v
# Loading C:/Documents and Settings/keshago/Desktop/resource/parts_lib.flop
# Loading C:/Documents and Settings/keshago/Desktop/resource/parts_lib.FDCE_1
# ** Error: (vsim-3043) C:/Documents and Settings/keshago/Desktop/resource/FDCE_1.v(39): Unresolved reference to 'glbl'.
# Region: /tesflop_v/uut/FDCE_1_inst
# Error loading design



The error details are
verror 3043
#
# vsim Message # 3043:
# The specified name in a simple or hierarchical reference cannot be found
# as an instance or object in the design.
#


But When i invoked the modelsim from ise i am able to simulate the design.

Can any body help me in this regard!

Thanks In advance
Keshav
 

keano

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modelsim glbl

can you share your source files?
I think i can help you.
 

echo47

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modelsim unresolved reference to

Unresolved reference to 'glbl'
Your list of ModelSim HDL project files should also include $XILINX/verilog/src/glbl.v
$XILINX is the environment variable pointing to your ISE installation

For more info, search your ISE "Synthesis and Simulation Design Guide" for the word glbl.v
Also try searching the Xilinx web site for the words modelsim and glbl.v
 

cherukukeshav

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error: (vsim-3043)

thanks for ur response.. Problem solved .. details are

VLOG Model Sim (vsim-3043) Unresolved reference to 'glbl'.


IF we use Verilog device primitives in Xilinx ISE and use those modules to run in Model Sim by creating separate project. We face the error unresolved reference to glbl.v

The global set/reset and global tristate signals are defined in the $XILINX/verilog/src/glbl.v module.

Follow the steps to simulate the modules which use the Xilinx device primitives
1. Instantiate the glbl module in the test bench.
2. Compile all used Xilinx device primitives including the “glbl.v” in the work library.
3. After compilation, select the glbl and the test bench file simultaneously and simulate.
4. Select the required signals to view.
5. Then run the simulation.


This will help to those who are got stuck with this problem.
There may be some other way to give reference of glbl.v file.

--Keshav
 

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