Problem with modelsim 6.5 from xilinx 7.1i

[rosem]

Hello,

When i try to have a behaviral or any simulation model to my Vhdl code in xilinx ise 7.1i, the modelsim opened and i get this pop-up saying :
""" unable to checkout a viewer license necessary for use of the modelsim graphical user interface. vsim is closing """ and then ok and it's closed.

I have set environment variables with the path : C:/FlexLm/license.DAT and i verified with "licensing wizard" and it's ok

Please can somebody help me !!!!
Thanks in advance

 

[TrickyDicky]

Yes. Start by getting a newer version. That software is at least 6 years old!

 

[rosem]

Yes. Start by getting a newer version. That software is at least 6 years old!

Thanks for the reply, actually i'm trying on xilinx 7.1i and in parallel on xilinx design suite 14.2. It worked with 14.2 but i didn't knew how to make a timing simulation which show a shift between the input and the output.
Is the post route simulation which show this shift ?? Because in my waveform it doesn't exist ?
Can you help me ?
Thank you :smile:

 

[TrickyDicky]

Do you have a good testbench? for 99% of good designs you only need to do a full RTL simulation and if you have use good design practice and a good set of timing constraints you dont need to do a timing simulation. The fact you ask about a "delay" between input and output makes me think you dont have a synchronous design.