problem with ISE6.1 synthesizer

[Vonn]

I have written a code in VHDL , this code contains n inout data bus
I have 2 problems when Iam trying to synthize using ISE

1- Even If I declare the data as inout port in the entity , the synthizer
force it to be output port ???
The only way to make the synthizer understand that it's an inout that
to write 'Z" to it in the code ???

2- When Iam trying to synthize ,I have the following error :

WARNING:Xst:1710 - FF/Latch <Mtridata_data_0> (without init value) is constant in block <testidts2>.
WARNING:Xst:638 - in unit testidts2 Conflict on KEEP property on signal Mtridata_data<15> and Mtridata_data<1> Mtridata_data<1> signal will be lost.

can any body give me a hand ?

another question . what (Mtridata) mean ?

 

[gnomix]

I have written a code in VHDL , this code contains n inout data bus
I have 2 problems when Iam trying to synthize using ISE

1- Even If I declare the data as inout port in the entity , the synthizer
force it to be output port ???
The only way to make the synthizer understand that it's an inout that
to write 'Z" to it in the code ???

2- When Iam trying to synthize ,I have the following error :

WARNING:Xst:1710 - FF/Latch <Mtridata_data_0> (without init value) is constant in block <testidts2>.

WARNING:Xst:638 - in unit testidts2 Conflict on KEEP property on signal Mtridata_data<15> and Mtridata_data<1> Mtridata_data<1> signal will be lost.
can any body give me a hand ?

another question . what (Mtridata) mean ?

It is very hard answer to your question without know the source code.

if it isn't a problem please share the source code so we can analyze it.

 

[Hero]

Hi,

Be ware if you are using bidirectional ports. Also you must understand that not all VHDL code is synthesizable.

Some parts of VHDL language you can use only for simulation not for synthesis.

So first check is your VHDL code synthesizable. Check architecture of taget device. Maybe your design is not possible for that target, e.g you want to use asynchronous reset on device wich don't have it. In that case problem is not in sythesizer, because design is not possible on that device.

 

[skynet]

Have you set the the i/o port direction in ISE6.1??

 

[Vonn]

the VHDL code is written to drive a certain chip
this part of code is used to make a write cycle command
----------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity IDTini is
Port ( masterreset : in std_logic;
masterclock : in std_logic;
infp : in std_logic;
inclk : in std_logic;
outled : out std_logic;
outled2 : out std_logic;
outfp : out std_logic;
outclk : out std_logic;
clk : out std_logic;
fp : out std_logic;
rst : out std_logic;
ode_1 : out std_logic;
ds : out std_logic;
cs : out std_logic;
r_w : out std_logic;
dta : in std_logic;
address : out std_logic_vector(15 downto 0);
data : inout std_logic_vector(15 downto 0));
end IDTini;

architecture Behavioral of IDTini is

signal currentstate,nextstate : integer ;
signal countMBP : integer ;
signal reading : std_logic_vector(15 downto 0);

begin
outfp <= infp ;
outclk <= inclk ;
clk <= inclk ;
fp <= infp ;
-------------------------------------------
process (masterclock,masterreset)
begin
If (masterreset='1') then
currentstate <= 0;
elsif (masterclock ='1' and masterclock'event) then
currentstate <= nextstate ;
else
end if ;
end process ;
--------------------------------------------
--------------------------------------------
process ( currentstate,dta )
Begin
Case currentstate is
when 0 =>
rst <= '0'; -- reset the chip and prepare the other ports
ode_1 <= '0' ;
ds <= '1' ;
cs <= '1' ;
r_w <= '0' ;
address <= "0100000000000000";
data <= "ZZZZZZZZZZZZZZZZ";
countMBP <= 3 ;
outled <= '0' ;
outled2 <= '0' ;
nextstate<= 1;

when 1 =>
rst <= '1' ;
data <= "0000000000000000";
cs <= '0' ;
nextstate <= 2 ;

when 2 =>
ds <= '0' ;
nextstate <= 3 ;

when 3 =>
if (dta ='0') then
nextstate <= 4 ;
else
nextstate <= 3 ;
end if ;

when 4 =>
ds <= '1' ;
nextstate <= 5 ;

when 5 =>
if (dta ='1') then
nextstate <= 6 ;
else
nextstate <= 5 ;
end if ;

when 6 =>
cs <= '1';
nextstate <= 7 ;

when others =>
End case ;
End process ;
--------------------------------------------
end Behavioral;
---------------------------------------------


NOW when you try to synthize this code you will have :
WARNING:Xst:1710 - FF/Latch <Mtridata_data_13> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<15> Mtridata_data<15> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_15> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<14> Mtridata_data<14> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_14> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<0> Mtridata_data<0> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_0> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<1> Mtridata_data<1> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_1> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<2> Mtridata_data<2> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_2> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<3> Mtridata_data<3> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_3> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<4> Mtridata_data<4> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_4> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<5> Mtridata_data<5> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_5> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<6> Mtridata_data<6> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_6> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<7> Mtridata_data<7> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_7> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<8> Mtridata_data<8> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_8> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<9> Mtridata_data<9> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_9> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<10> Mtridata_data<10> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_10> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<11> Mtridata_data<11> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_11> (without init value) is constant in block <idtini>.
WARNING:Xst:638 - in unit idtini Conflict on KEEP property on signal Mtridata_data<13> and Mtridata_data<12> Mtridata_data<12> signal will be lost.
WARNING:Xst:1710 - FF/Latch <Mtridata_data_12> (without init value) is constant in block <idtini>.


ANY BODY CAN HELP ?

 

[r_e_m_y]

Hi,

Your data bus is considered as an outuput by the synthesizer because you never take into account the value of data as an input. You only use it as an output (ex : data <= "1000ZZ00".
You should have an equation like : memorized_data <= data; in your vhdl to use data as an input.

I think that you should use a latch signal for your data, not only combinatory :

process (masterclock,masterreset)
begin
If (masterreset='1') then
currentstate <= 0;
data <= (others => 'Z');
elsif (masterclock ='1' and masterclock'event) then
currentstate <= nextstate ;
out_latch_data <= out_comb_data;
else
end if ;
end process ;

data <= out_latch_data when (output_enable = '1') else (others => 'Z');

--------------------------------------------
process ( currentstate,dta )
Begin
Case currentstate is
when 0 =>
rst <= '0'; -- reset the chip and prepare the other ports
ode_1 <= '0' ;
ds <= '1' ;
cs <= '1' ;
r_w <= '0' ;
address <= "0100000000000000";
out_comb_data <= "ZZZZZZZZZZZZZZZZ";
countMBP <= 3 ;
outled <= '0' ;
outled2 <= '0' ;
nextstate<= 1;

when 1 =>
rst <= '1' ;
...


I did not try this but I think i will work
I hope this will help you
:wink:

 

[bibo1978]

declaration of an inout port in VHDL doesn't mean that the synthezer will understand that it is an inout port, so to do an inout port "say it's name data", you will have to declare two signals "data_in and data_out" the signal data-in will be the input data from the inout port and this will be declared in you VHDL code as "data_in <= data;", the data out is the output data which mus be controlled with a tr-state buffer "because you can't read when you are writing". so the data bus will be data-out when you have and enable signal let us name this signal as "en", so the code to install the tri-state bufffer will be "data <= data_out when en='1' else (OTHERS=>'Z');"
that's all folks