Problem with inout in verilog for my program

[Damomeera]

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Code Verilog - [expand]
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module REG_BANK(M_O,A_IO,SEL,A_EN,M_EN,RW,CLOCK
    );
    output [7:0] M_O;
     inout [7:0] A_IO;
     input [2:0] SEL;
    input A_EN, M_EN, RW, CLOCK;
     
     reg [7:0] M_O, A_I;
     reg [7:0] memblk [0:7];
     
     assign A_IO = ( A_EN == 1'b1 && RW == 1'b0 )? A_I : A_IO;  // NOT WORKING NOT UPDATING THE A_IO VALUE
     
     always @( posedge CLOCK )
     begin
              if( M_EN == 1'b0 )
                    M_O = 8'b00000000;
              else if( M_EN == 1'b1 && RW == 1'b0 )
           begin
                    case ( SEL )
                      3'b000 : M_O = memblk[0]; 
                      3'b001 : M_O = memblk[1];
                      3'b010 : M_O = memblk[2];
                      3'b011 : M_O = memblk[3];
                      3'b100 : M_O = memblk[4];
                      3'b101 : M_O = memblk[5];
                      3'b110 : M_O = memblk[6];
                      3'b111 : M_O = memblk[7];
                      endcase
           end  
 
           if( A_EN == 1'b0 )
           begin
                  
              end     
           else if( A_EN == 1'b1 && RW == 1'b0 )
           begin
                    case ( SEL )
                      3'b000 : A_I = memblk[0]; 
                      3'b001 : A_I = memblk[1];
                      3'b010 : A_I = memblk[2];
                      3'b011 : A_I = memblk[3];
                      3'b100 : A_I = memblk[4];
                      3'b101 : A_I = memblk[5];
                      3'b110 : A_I = memblk[6];
                      3'b111 : A_I = memblk[7];
                      endcase
           end            
              else if( A_EN == 1'b1 && RW == 1'b1 )
           begin
                    case ( SEL )
                      3'b000 : memblk[0] = A_IO; 
                      3'b001 : memblk[1] = A_IO;
                      3'b010 : memblk[2] = A_IO;
                      3'b011 : memblk[3] = A_IO;
                      3'b100 : memblk[4] = A_IO;
                      3'b101 : memblk[5] = A_IO;
                      3'b110 : memblk[6] = A_IO;
                      3'b111 : memblk[7] = A_IO;
                      endcase
           end            
    end
 
endmodule

---

In the above program the A_IO value doesn't get updated during A_EN = 1 and RW = 0.
Pls help me.

 

[FvM]

An inout port must be driven to z state if you want to read it as an input.

 

[StanDarsh18]

Check out this thread for help with the inout port.

https://www.edaboard.com/threads/313198/

 

[Damomeera]

There is no problem in reading the inout port.
I didn't get new values according to the assign statements

- - - Updated - - -

An inout port must be driven to z state if you want to read it as an input.

This is the output i got. pls help me sir.

- - - Updated - - -

Check out this thread for help with the inout port.

https://www.edaboard.com/threads/313198/

Thanks

- - - Updated - - -

Check out this thread for help with the inout port.

https://www.edaboard.com/threads/313198/

---

Code Verilog - [expand]
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module TOP;
 
wire [7:0] m_o;
wire [7:0] a_io;
reg [7:0] a_i;
reg [2:0] sel;
reg a_en, m_en, rw, clk;
 
REG_BANK r ( m_o, a_i0, sel, a_en, m_en, rw, clk );
 
 
initial 
begin
 
a_en = 1'b0;m_en = 1'b0; 
#20 a_en = 1'b1; rw = 1'b1; sel = 3'b000; a_i = 8'b00101011;
#20 a_en = 1'b1; rw = 1'b1; sel = 3'b001; a_i = 8'b00101100;
#20 a_en = 1'b1; rw = 1'b1; sel = 3'b010; a_i = 8'b10000111;
#20 a_en = 1'b1; rw = 1'b1; sel = 3'b011; a_i = 8'b10101101;
#20 a_en = 1'b1; rw = 1'b1; sel = 3'b100; a_i = 8'b11111001;
#20 a_en = 1'b1; rw = 1'b1; sel = 3'b101; a_i = 8'b10101111;
#20 a_en = 1'b1; rw = 1'b1; sel = 3'b110; a_i = 8'b10000111;
#20 a_en = 1'b1; rw = 1'b1; sel = 3'b111; a_i = 8'b10100111;
#20 rw = 1'b0; sel = 3'b010; a_en = 1'b1;
#20 a_en = 1'b0; m_en = 1'b1; sel = 3'b011; 
 
end
 
initial 
begin
 
 
#400 $finish;
 
end
 
initial 
begin
 
clk = 1'b0;
forever #20 clk = ~ clk;
 
end
 
endmodule

---

it's stimulus module for the above module.
how to assign values to inout port

- - - Updated - - -

Sorry Bro

I want to design a register bank with one inout port and one output port.

 

[ads-ee]

I want to design a register bank with one inout port and one output port.

If you are using an inout then this register bank better be interfacing with an external device as inout can only be represented by a bidirectional I/O pin.

If it's an internal signal you shouldn't be using inout.

Regards

 

[FvM]

assign A_IO = ( A_EN == 1'b1 && RW == 1'b0 )? A_I : 8'bz;