Problem with initial statement in a testbench code

i have a prblm with my testbench.i have written my testbench correctly.but it is not working.prblm is in the code i wrote initial statement like this
y=b;
b is my primary out,y initialized as a reg
prblm is my test bench unable to assign my b value to the variable y .
why this happening.wen i replaced initial with always it is working fine.why?

test bench problem

Please post the whole code here. It is rather complicated task to answer to your question based only on this description.

test bench problem

Because this statement is only execute once at the start of simulation.
your design is not prepare the correct value on the simulation time 0.

test bench problem

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Added after 6 minutes:

module booths( a,b,clk,z);
input[7:0] a,b;
input clk;
//output [15:0] c;
output [24:0] z;
reg [24:0] z;
reg [7:0] y;
reg[15:0] c;
integer i=0;
initial
begin
y=b;
z[24:9]=16'b0;
z[8:1]=a;
z[0]=0;
y=~y;
y=y+1'b1;

end




always@(posedge clk )
begin

if(i<8)
begin
case (z[1:0])
2'b00:
begin
z[8:0]=z[8:0]>>1;
z[8]=z[0];
z[24:9]=z[24:9]>>1;
z[24]=z[23];
end

2'b11 :
begin
z[8:0]=z[8:0]>>1;
z[8]=z[0];
z[24:9]=z[24:9]>>1;
z[24]=z[23];
end
2'b01 :
begin
z[24:17]=z[24:17]+ b;
z[8:0]=z[8:0]>>1;
z[8]=z[0];
z[24:9]=z[24:9]>>1;
z[24]=z[23];
end
2'b10 :
begin
z[24:17]=z[24:17] + y;
z[24:0]=z[24:0]>>1;
z[24]=z[23];
z[8]=z[0];
end
endcase

end

i=i+1;
c[15:0]=z[24:9];
end
endmodule




//=====================================================
//test bench for booths multiplier:



module boothstest;
reg [7:0] a,b;
reg clk;
wire [24:0] z;

booths b2(a ,b, clk, z); //module instantiation.......................

initial
begin
a=0;
b=0; //initializating inputs,clock................
clk=0;
end

always
#5 clk=~clk;

initial
begin
#5 a=10; b=20; //applying stimuli..............................
#100 $stop;
end

initial
$monitor($time,"out = %b",z);

endmodule

Re: test bench problem

Hi Nikhil,
If the "booth" is supposed to be your "design" code, then it should avoid using initial construct. Use always block - initial executes just once and hence you got that result.

Nikhil said:

Code:

 module booths( a,b,clk,z);
input[7:0] a,b;
input clk;
//output [15:0] c;
output [24:0] z;
reg [24:0] z;
reg [7:0] y;
reg[15:0] c;
integer i=0;
		initial
			begin
  						y=b;
 						z[24:9]=16'b0;
 						z[8:1]=a;
 						z[0]=0;
 						y=~y;
 						y=y+1'b1;
 					
 			end


		
		
		always@(posedge clk ) 
			begin
				
					      if(i<8)
						     begin
								case (z[1:0])
									2'b00: 
										begin
										z[8:0]=z[8:0]>>1;
        										z[8]=z[0];
        										z[24:9]=z[24:9]>>1;
        										z[24]=z[23];
   										end
   
									2'b11 :
										begin
        										z[8:0]=z[8:0]>>1;
        										z[8]=z[0];
        										z[24:9]=z[24:9]>>1;
        										z[24]=z[23];
   										end
									2'b01 :  
										begin
										z[24:17]=z[24:17]+ b; 
										z[8:0]=z[8:0]>>1;
										z[8]=z[0];
										z[24:9]=z[24:9]>>1;
										z[24]=z[23];
        										end
									2'b10 :  
										begin
										z[24:17]=z[24:17] + y;
										z[24:0]=z[24:0]>>1;
										z[24]=z[23];
										z[8]=z[0];
        										end       
   								endcase
   
  						    end
   					
   				i=i+1;
 				c[15:0]=z[24:9];
			end
endmodule

Click to expand...

I would recommend you read good Verilog book and also try a decent lint tool such as Spyglass or Leda.

Regards
Ajeetha, CVC
www.noveldv.com

nikhilindia85 said:

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Added after 6 minutes:

Click to expand...