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Problem with Initial State of FF on Xilinx

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Member level 2
May 31, 2001
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Hi All,

I'm using HdlDesigner to describe a circuit for Xilinx Virtex-4, and I found something really strange. The problem is on the VHDL code bellow:

if (aq_clk'event and aq_clk ='1') then
we_hd <= st_nr_hd_a or st_nr_hd_b or st_rnd_hd_a or st_rnd_hd_b;
we_hd_r <= we_hd;
end if;

This code should be converted into two FF's and some logic.
The problem is that the tools create a FF (named we_hd) with INIT=1 and another FF (named we_hd_r) with INIT=0.

Since I cannot go on all FF's and see whats the INIT property does any one have a possible explanation for this?
NOTE: There is No other property applied to signals above that could cause the different behavior.

Thank you very much for your comments.
Best Regards

Well I do not have to the point answer to your question, but I am wondering why do you care? You haven't applied any reset to your registers, so weather they are initialised to '0' or a '1', should not make you feel uncomfortable?. and if you do care, then try putting an init value to the regs.
Here is how u do it
attribute init of {component_name|label_name|signal_name}: {component|label|signal} is “value”;
More can be found at:
**broken link removed**
Hope it helps.

Hi Avi,

The reason because I care is that we_hd_r is a Write Enable of a FIFO that CANNOT be active during reset OR flags will go wild. (Thats what is currently happening).
I can make some changes to the design to avoid the problem, BUT the main problem is: How do I know that this problem is not present in another FF... that will cause some unexpected behavior? And more important: Where is decided that a given FF starts HI or LOW?

Thank you for your help.
Best Regards

Again I dont know why it is happening. BUT,
by design, you should not have any flip flops, undefined at the start up, if they are cticial for the funtionality.
As if a register is a wirte_enable to a fifo, then this register MUST not be coded, without having a defined reset going on to it.
Its not one of the best practices to leave these registers at the mercy of xilinx or any other tool.
Think, if you dont put a reset to the 'critical' registers in a design, then at power up they may take up any value, and kill your funcionality. Well this is what happens in ASIC, for FPGA I am not sure, may be xilinx put random init values to the registers not defined at power up or having no reset at all. And that is why you are having different init values for different registers in your design.
A better design will always be well thought of and will NOT have any critical register uninitialized.

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