module tirtik_hafiza3
(
input wire clock
,input wire reset
,input wire [06:00] tirtik
,input wire read_write
,output reg read_write_led
,output reg [06:00] mem_led
);
reg [6:0] mem [100:0];
reg [7:0] address;
reg change;
// integer i;
reg [06:00] rst_counter;
reg rst, rst_f1;
always @ (posedge clock)
begin
if (reset)
rst <= 1'b1;
else if (rst_counter == 7'h63)
rst <= 1'b0;
end
always @ (posedge clock)
begin
rst_f1 <= rst;
end
always @ (posedge clock)
begin
if ((rst)&&(~rst_f1))
begin
rst_counter <= {7{1'b0}};
end
else
begin
if (rst_counter == 7'h64)
rst_counter <= 7'h64;
else
rst_counter <= rst_counter + 1'b1;
end
end
always @ (posedge clock)
begin
if(rst)
begin
address <= 8'h0;
change <= 1;
mem[rst_counter] <= 7'b0000000;
mem_led <= 7'b0000000;
end
else if(read_write)
begin
read_write_led <= 1;
address <= address +1;
change <= 1;
mem[address] <= tirtik;
end
else if (!read_write)
begin
if(!change)
begin
read_write_led <= 0;
mem_led <= mem[address];
address <= address +1;
end
else
begin
address <= 0;
change <= 0;
end
end
end
endmodule