problem with finding input and output transistors in a spice netlist

[mostafa272]

Hi

I wrote a ALU with Verilog code,then I made tpr file from it,and in next step I created it's layout in L-Edit. Now, I like to extract it's netlist from layout,but the count of transistors is very very many and I don't know which of them are input transistors and which of them are output transistors.How can I label input and output transistors? please help me.

 

[artmalik]

The spice netlist has a definite order in which mosfet ports are defined : G D S B. The output ports are named according to your netlist. The internal nets can have random names or names which are there in the prelayout netlist depending upon the capabilities of your extraction tool.

 

[mostafa272]

I work with L-Edit to create Layout and extract netlist from it. It creates name of transistors automatically when I try to extract spice netlist. the count of transistors is very many, and I can not find input and output transistors from layout or netlist.please show me a good way!