Vonn
Full Member level 4
VHDL Problem
Hi all ,
I'm writing VHDL code to drive a programmable chip. My problem is that when I define the Inout port the synthiezer force it to out port . The only way to make it understand that it's an INout that you must load it by 'Z' during the code ...
My questionis , is that the only solution ??
Hi all ,
I'm writing VHDL code to drive a programmable chip. My problem is that when I define the Inout port the synthiezer force it to out port . The only way to make it understand that it's an INout that you must load it by 'Z' during the code ...
My questionis , is that the only solution ??