synopsis fpga express can except:
a small skeleton if you want a bidirectional bus/port:
entity fpga is
port(
...
bus : inout Std_Logic_Vector(n downto 0);
rd_neg: in Std_Logic;
...
);
end fpga;
architecture fpga_arch of fpga is
-- signals for the internal registers
busin : Std_Logic_Vector(n downto 0);
busout : Std_Logic_Vector(n downto 0);
....
busin <= bus;
bus <= busout when rd_neg = '0' else (others => 'Z');
end fpga_arch;
if you want just a feedback from an out port, maybe, you'd better define an internal signal to avoid inout:
entity fpga is
port(
...
porty : out Std_Logic;
...
);
end fpga;
architecture fpga_arch of fpga is
porty_s : Std_Logic;
...
porty_s <= ...; -- get the out value
porty <= porty_s; -- create the output
... <= porty_s; -- use as input
end fpga_arch;