pocho
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I have a problem with the for loop.
In this piece of code I would check two vectors of length
32-bit. With the for loop control vectors bit by bit, but the problem is that in the simulation control is only in the first bit does not control the other.
In this piece of code I would check two vectors of length
32-bit. With the for loop control vectors bit by bit, but the problem is that in the simulation control is only in the first bit does not control the other.
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_textio.ALL;
use std.textio.all; -- utilizzo del file txt
entity testbench_adder_32bit is
generic (T0: time:= 10 ns;
period: time:= 200 ns);
port (
A, B: out std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32); -- li setto a 0
Cin: out std_logic := '0';
S: in std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32);
Cout: in std_logic := '0'
);
end testbench_adder_32bit;
architecture testbench_carry_select_adder_32bit of testbench_adder_32bit is
type test_vector_type is array (0 to 9) of std_logic_vector (31 downto 0);
signal j: integer := 0;
signal k: integer := 0;
signal c: integer := 0;
signal max_carry_chain: integer := 0;
signal semaforo: std_logic :='0';
signal reference_clock: std_logic := '0';
signal T0_clock: std_logic := '0';
signal T0_Cout: std_logic := '0';
signal T0_reg: std_logic_vector (31 downto 0) := conv_std_logic_vector(0,32);
signal test_vector_1: test_vector_type;
signal test_vector_2: test_vector_type;
signal test_vector_length: integer := 0;
signal A_carry, B_carry: std_logic_vector(31 downto 0):= conv_std_logic_vector(0,32);
begin
reference_clock <= not reference_clock after period/2.0;
T0_clock <= transport reference_clock after T0;
read_values: process
file fp: text open read_mode is "Addizione.vhd";
variable ln: line;
variable x, y: std_logic_vector (31 downto 0);
variable i: integer := 0;
begin
while not endfile( fp ) loop --fatta modifica Menichelli
readline( fp, ln );
read( ln, x );
read( ln, y );
test_vector_1(i) <= x;
test_vector_2(i) <= y;
i := i+1;
end loop;
test_vector_length <= i;
wait;
end process read_values;
input_generator: process (reference_clock)
begin
if reference_clock'event and reference_clock = '1' then
if j < test_vector_length then
A <= (test_vector_1(j));
B <= (test_vector_2(j));
A_carry <= (test_vector_1(j));
B_carry <= (test_vector_2(j));
j <= j+1;
elsif j = test_vector_length then
j <= j+1;
end if;
end if;
end process input_generator;
------------------------------------------------------------------------
carry: process (A_carry,B_carry)
begin
for k in 0 to 31 loop
if ((A_carry(k)= '1')) and ((B_carry(k)= '1')) then
semaforo <='1';
c <=c+1;
elsif ((A_carry(k)= '1') or (B_carry(k)= '1')) and (semaforo = '1') then
c <=c+1;
else
semaforo<='0';
c <=0;
end if;
end loop;
k<=0;
if max_carry_chain < c then
max_carry_chain<=c;
end if;
end process carry;
-----------------------------------------------------------------------
write_result: process( reference_clock )
file fpo: text open write_mode is "test_result.txt";
variable lno: line;
variable xo: bit_vector(31 downto 0);
variable yo: std_logic;
begin
if reference_clock'event and reference_clock = '1' then
if j/=0 and j<=test_vector_length then
xo := to_bitvector( S );
write( lno, xo );
writeline( fpo, lno );
yo := Cout;
write( lno, yo );
writeline( fpo, lno );
end if;
end if;
end process write_result;
end testbench_carry_select_adder_32bit;
