nemuri
Newbie level 6
hi,
i am faced with a strange behaviour of this UTMI, maybe someone have already seen this problem and know how to resolve it :
For sending data from an SIE to the PC via USB, I use the UTMI. I have problems with the Tx register
I assert the Txvalid signal to indicate that i want to send data.
then, when the UTMI is ready, it asserts the TxReady signal and load the data at the rising edge of the clock (60 MHz clock, provided by the UTMI itself)
I am working in 8 bit bidir, full speed, so normally, the Txready signal is negated as soon as the data is loaded, and saty negated until the data is sent. Then TxReady will be asserted again for the next data, ect.
The problem is that in my case, Txready stays asserted for 2 clocks period. Hence, the data is loaded twice, and sent twice on the USB.
That confuses me, because Txready is a signal provided by the UTMI, as well as the clock, so how come it is not shaped as supposed ?
I can't modify those signals, so i don't know what i can do. I changed the part and the problem is the same. Cypress reminds vague and answer my question by quoting the spec (as if i hadn't read it...)
So, any idea anyone ?
i am faced with a strange behaviour of this UTMI, maybe someone have already seen this problem and know how to resolve it :
For sending data from an SIE to the PC via USB, I use the UTMI. I have problems with the Tx register
I assert the Txvalid signal to indicate that i want to send data.
then, when the UTMI is ready, it asserts the TxReady signal and load the data at the rising edge of the clock (60 MHz clock, provided by the UTMI itself)
I am working in 8 bit bidir, full speed, so normally, the Txready signal is negated as soon as the data is loaded, and saty negated until the data is sent. Then TxReady will be asserted again for the next data, ect.
The problem is that in my case, Txready stays asserted for 2 clocks period. Hence, the data is loaded twice, and sent twice on the USB.
That confuses me, because Txready is a signal provided by the UTMI, as well as the clock, so how come it is not shaped as supposed ?
I can't modify those signals, so i don't know what i can do. I changed the part and the problem is the same. Cypress reminds vague and answer my question by quoting the spec (as if i hadn't read it...)
So, any idea anyone ?