Problem with correct configuration of FPGA and PROMs (cascaded)

[Veronika]

I need to configure one FPGA and two Platform Flash memories.
I have found the following example: UG161.pdf, page 44, Figure 5-1.
There are two FPGAs - Master and Slave. But I am going to use Master FPGA only.
How changes the configuration setup in my case? Or I can simply ignore Slave FPGA in the Figure 5-1?

 

[barry]

"UG161.pdf" doesn't mean anything to anybody. Do you have a link?

I assume this is a JTAG chain?

 

[mrflibble]

https://www.xilinx.com/support/documentation/user_guides/ug161.pdf

But yeah, next time give a link. Saves us having to assume you mean a xilinx user guide.

 

[ads_ee]

Just leave the slave FPGA device off. The platform flash allows for one device enabling a second device after the first has finished outputting all of it's data.