Buriedcode
Full Member level 6
adc dac jitter
Hi, I've posted here before and people were very helpful, and knowlegable
.
First of all, I'm sorry if this is the wrong place to post this, but it is to do with digital interface.
Basically, I've created a wireless digital audio system, using PLD's, I haven't started the wireless part yet, just wanted to see if I could effectively convert audio to the digital domain and back again first.
I don't want to go into to much detail, but I suppose you do need to know the system if you are to help me identify the problem
basic overview:
TX: analogue buffer -> ADC -> CPLD -> output.
Rx: input -> CPLD -> DAC -> analogue buffer.
In both the TX and RX the CPLD and the ADC/DAC are run off of the same clock, a 12.288Mhz clock oscillator module with low jitter, connected DIRECTLY to both without a buffer (the CPLD has a built in clock buffer).
Now. I'm convinced that there is nothing wrong with my program in controlling the ADC/DAC, and the analogue part has been thoroughly tested, and is fine. So this isn't a VHDL question
When the system starts, if the RX is on, but it doesn't receive a signal from the TX, then the RX is designed NOT to start the DAC (ie, not only does it not write data to it, it doesn't even power it up). And as long as the RX receives a signal, in a specific format which is unique to the TX (format being, start/stop bits being in the write place and the right time) the CPLD in the RX starts writing data to the DAC.
Now, it does work, in the fact that when both units are on and connected, the CPLD in the RX controls the DAC nicely, checked with a high-speed oscilloscope. But.... ....the output audio from the DAC in the RX is just really loud periodic noise. SHSH....SHSHS....SHSH with a period of about 0.8seconds. Now, one simple test I did was to ground the DATA pin on the DAC, this means that the only thing written to the DAC is all 0's. The DAC is a 2's compliment device so this equates to about -V, but its not changing so the output should be completely silent, and it IS.
Basically, my question is about interfaces.
Should I use a clock buffer before the ADC?
Are Sigma-delta ADC's very sensitive to clock jitter, clock shape, rise time?
Are these clock oscillator modules any good for this application (model number CMAC IQXO-350-12.288)
And finally, has anyone had experience with using the CS5330A and the CS4330A from cirrus logic?
I'm sorry if this is a bit pointless and long, but any advice and previous experiences regarding any of the subjects covered will be very welcome.
Thankyou for your time.
BuriedCode :roll:
Hi, I've posted here before and people were very helpful, and knowlegable
.First of all, I'm sorry if this is the wrong place to post this, but it is to do with digital interface.
Basically, I've created a wireless digital audio system, using PLD's, I haven't started the wireless part yet, just wanted to see if I could effectively convert audio to the digital domain and back again first.
I don't want to go into to much detail, but I suppose you do need to know the system if you are to help me identify the problem
basic overview:
TX: analogue buffer -> ADC -> CPLD -> output.
Rx: input -> CPLD -> DAC -> analogue buffer.
In both the TX and RX the CPLD and the ADC/DAC are run off of the same clock, a 12.288Mhz clock oscillator module with low jitter, connected DIRECTLY to both without a buffer (the CPLD has a built in clock buffer).
Now. I'm convinced that there is nothing wrong with my program in controlling the ADC/DAC, and the analogue part has been thoroughly tested, and is fine. So this isn't a VHDL question
When the system starts, if the RX is on, but it doesn't receive a signal from the TX, then the RX is designed NOT to start the DAC (ie, not only does it not write data to it, it doesn't even power it up). And as long as the RX receives a signal, in a specific format which is unique to the TX (format being, start/stop bits being in the write place and the right time) the CPLD in the RX starts writing data to the DAC.
Now, it does work, in the fact that when both units are on and connected, the CPLD in the RX controls the DAC nicely, checked with a high-speed oscilloscope. But....
....the output audio from the DAC in the RX is just really loud periodic noise. SHSH....SHSHS....SHSH with a period of about 0.8seconds. Now, one simple test I did was to ground the DATA pin on the DAC, this means that the only thing written to the DAC is all 0's. The DAC is a 2's compliment device so this equates to about -V, but its not changing so the output should be completely silent, and it IS.Basically, my question is about interfaces.
Should I use a clock buffer before the ADC?
Are Sigma-delta ADC's very sensitive to clock jitter, clock shape, rise time?
Are these clock oscillator modules any good for this application (model number CMAC IQXO-350-12.288)
And finally, has anyone had experience with using the CS5330A and the CS4330A from cirrus logic?
I'm sorry if this is a bit pointless and long, but any advice and previous experiences regarding any of the subjects covered will be very welcome.
Thankyou for your time.
BuriedCode :roll: