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[SOLVED] problem with conditional operator in verilog

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arishsu

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Is this syntax is right for 4:1 mux output?

assign Y=(S==0x)?((S==00)? I[0]:I[1]):(((S==1x)?((S==10)? I[2]:I[3]));

S is 2 bit reg(select line), I is 4 bit reg(input) and Y output.
 

mrflibble

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Best get rid of the x don't cares. See this thread for some examples.

Personally I use something like this:
Code:
assign o= (s[0]==0)?((s[1]==0)?i[0]:i[1]):((s[1]==0)?i[2]:i[3]);
 

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Best get rid of the x don't cares. See this thread for some examples.

Personally I use something like this:
Code:
assign o= (s[0]==0)?((s[1]==0)?i[0]:i[1]):((s[1]==0)?i[2]:i[3]);

A little formatting might make it more readable...


Code Verilog - [expand]
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assign o = (s[0]==0) ? ([s[1]==0) ? i[0]   // 00
                                  : i[1])  // 10
                     : ((s[1]==0) ? i[2]   // 01
                                  : i[3]); // 11

 

mrflibble

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A little formatting might make it more readable...

Fully agreed. I was just reciprocating laziness, and as such did a quick copy/paste from that other thread with the kind of code snippet I'd use. ;)
 

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