hi all
i've written a behaviour description og IIR filter in VHDL and use
wait on clk until clk='1'
during synthesis with xilinx it is giving error and expecting exit after wait.is this neccessary to give this.in compilation there was no error in the code.
kindly give your valuable suggestions
hi
thanks for reply.but i've not used sensitivity list in process.process doesn't have any sensitivity list so i used wait statement.and in IIR filter i think we don't have to include clk in sensitivity list
main_loop:loop
wait on clk until clk='1';
lad_coeff:for i in 2*order downto 0 loop
coeff_prog(i):=coeffin;
wait on clk until clk='1';
end loop;
new_coeff<='0';
wait on clk until clk='1';
filter:for i in count-1 downto 0 loop
hshk_loop:while(enable='0') loop
wait on clk until clk='1';
end loop;
Hi smith_kang,
I guess the wait statements in VHDL are not synthesisable. they are used for behavioral modfelling only. Recode your logic based on standard templates provided by your synthesis tool.
Sorry to say but this code is definitely not synthesizable!
HDL means "Hardware Description Language" So first you
think about the hardware and to describe it use HDL.
You seems to be new to VHDL and logic synthesis.
Thanks nand_gates to remind me.I'm not new to VHDL but from last few months i was trying to implement synchronous logics.thats why.
thanks again to remind me.