Problem with assigning a generic

[satty_008]

I am relatively new to VHDL and am facing problems with generics. I want to assign a signal value to a generic .
Is it possible?
architecture rtl of entity_name is
signal ibaudratetop: integer;


component my_baud1 is
generic(
baudrate : integer := 115200;
clock_freq_mhz : real := 1.843200
);
port(
clk : in std_logic;
rst : in std_logic;
baud : out std_logic
);
end component;

begin
BAUDRATE: my_baud1
generic map(
baudrate =>ibaudratetop,
clock_freq_mhz => 1.843200
)
port map(
clk =>clk,
rst =>rst,
baud =>ibaudrx
);
end rtl

This is only a part of my UART code...Please have a look at the like which is in BOLD and help.Is that type of generic mapping possible where a signal which is of type integer is assigned to a generic.? I am unable to simulate the code. Thanks in advance !!

 

[FvM]

According to the nature of generics, this is not possible. Generics are supplying design parameters that must be completely known at compile time.

You can only assign a constant expression to baudrate, it might refer to other generics.

 

[satty_008]

According to the nature of generics, this is not possible. Generics are supplying design parameters that must be completely known at compile time.

You can only assign a constant expression to baudrate, it might refer to other generics.

Thanks a lot.. so you mean to say there is no way other than to assign a constant to generic
? :?::|:-(