ismailov-e
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Hi everybody!!
I have a stuck to compare a portion of bytes of two registers.
I have a 2 register with 20 byts of width. The value of 1st registers always changes by loop. I want to compare only some portion of two register(let it be 64 bit, 8byte). But the length of comparing bits is variable(can change value). If i use a loop variable in indeces, the bag accur as it is a not a constant.
In this case i want to use only first 63 bits. Now "pattlen = 63"
I cant use bit-slice as the right site should be constant
I have a stuck to compare a portion of bytes of two registers.
I have a 2 register with 20 byts of width. The value of 1st registers always changes by loop. I want to compare only some portion of two register(let it be 64 bit, 8byte). But the length of comparing bits is variable(can change value). If i use a loop variable in indeces, the bag accur as it is a not a constant.
In this case i want to use only first 63 bits. Now "pattlen = 63"
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 initial begin if (state == C) begin pattlen = (countp*8)-1; for (i = 5; i < 15; i = i + 1)begin for (k = 0; k < 4; k = k + 1)begin buffshift[167:160] = slv_reg[i][(k*8)+:8]; buffshift[159:0] = buffshift[167:8]; if (buffpatt[pattlen:0] == buffshift[pattlen:0]) wordcount = wordcount + 1; $display("%b %d",buffshift,wordcount); end end end //state = D; end
I cant use bit-slice as the right site should be constant
Code Verilog - [expand] 1 if (buffpatt[0+:pattlen] == buffshift[0+:pattlen])