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Problem with a constant parameter in Verilog code

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Parameter in Verilog

I'm refine a design to be parameterized.
The code is now:
module #(w1, w2, w3, w4, w5, w6) all_mux
mux #(w1) mux_inst_1;
mux #(w2) mux_inst_2;
...

The goal to use generate. Replace w with w1, w2, ... w6. Something like:

module #(w1, w2, w3, w4, w5, w6) all_mux
genvar i
generate for (i=1; i< 7; i=i+1) mux #(w) mux_inst;
endgenerate;

The problem is w needs to be constant. While, I didn't figure out a way to make it happen.
Any ideas?
 

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