Jan 6, 2005 #1 M Monkey Newbie level 6 Joined Apr 26, 2004 Messages 13 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 118 Parameter in Verilog I'm refine a design to be parameterized. The code is now: module #(w1, w2, w3, w4, w5, w6) all_mux mux #(w1) mux_inst_1; mux #(w2) mux_inst_2; ... The goal to use generate. Replace w with w1, w2, ... w6. Something like: module #(w1, w2, w3, w4, w5, w6) all_mux genvar i generate for (i=1; i< 7; i=i+1) mux #(w) mux_inst; endgenerate; The problem is w needs to be constant. While, I didn't figure out a way to make it happen. Any ideas?
Parameter in Verilog I'm refine a design to be parameterized. The code is now: module #(w1, w2, w3, w4, w5, w6) all_mux mux #(w1) mux_inst_1; mux #(w2) mux_inst_2; ... The goal to use generate. Replace w with w1, w2, ... w6. Something like: module #(w1, w2, w3, w4, w5, w6) all_mux genvar i generate for (i=1; i< 7; i=i+1) mux #(w) mux_inst; endgenerate; The problem is w needs to be constant. While, I didn't figure out a way to make it happen. Any ideas?